diff options
Diffstat (limited to 'src/mem/cache')
-rw-r--r-- | src/mem/cache/base.cc | 2 | ||||
-rw-r--r-- | src/mem/cache/prefetch/base.cc | 4 | ||||
-rw-r--r-- | src/mem/cache/prefetch/base.hh | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/base.cc | 4 | ||||
-rw-r--r-- | src/mem/cache/tags/base_set_assoc.cc | 1 | ||||
-rw-r--r-- | src/mem/cache/tags/fa_lru.cc | 3 |
6 files changed, 10 insertions, 6 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 70d1b4167..faa000c09 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -67,6 +67,7 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, BaseCache::BaseCache(const Params *p) : MemObject(p), + cpuSidePort(nullptr), memSidePort(nullptr), mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, MSHRQueue_WriteBuffer), @@ -77,6 +78,7 @@ BaseCache::BaseCache(const Params *p) forwardSnoops(p->forward_snoops), isTopLevel(p->is_top_level), blocked(0), + order(0), noTargetMSHR(NULL), missCount(p->max_miss_count), addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc index 57c1424bf..971ecf5b0 100644 --- a/src/mem/cache/prefetch/base.cc +++ b/src/mem/cache/prefetch/base.cc @@ -57,7 +57,8 @@ #include "sim/system.hh" BasePrefetcher::BasePrefetcher(const Params *p) - : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree), + : ClockedObject(p), size(p->size), cache(nullptr), blkSize(0), + latency(p->latency), degree(p->degree), useMasterId(p->use_master_id), pageStop(!p->cross_pages), serialSquash(p->serial_squash), onlyData(p->data_accesses_only), onMissOnly(p->on_miss_only), onReadOnly(p->on_read_only), @@ -69,6 +70,7 @@ BasePrefetcher::BasePrefetcher(const Params *p) void BasePrefetcher::setCache(BaseCache *_cache) { + assert(!cache); cache = _cache; blkSize = cache->getBlockSize(); } diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh index fc0dd0b36..22a4c68f6 100644 --- a/src/mem/cache/prefetch/base.hh +++ b/src/mem/cache/prefetch/base.hh @@ -83,7 +83,7 @@ class BasePrefetcher : public ClockedObject BaseCache* cache; /** The block size of the parent cache. */ - int blkSize; + unsigned blkSize; /** The latency before a prefetch is issued */ const Cycles latency; diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc index 446c1ea49..2ec1379b0 100644 --- a/src/mem/cache/tags/base.cc +++ b/src/mem/cache/tags/base.cc @@ -56,13 +56,15 @@ using namespace std; BaseTags::BaseTags(const Params *p) : ClockedObject(p), blkSize(p->block_size), size(p->size), - hitLatency(p->hit_latency) + hitLatency(p->hit_latency), cache(nullptr), warmupBound(0), + warmedUp(false), numBlocks(0) { } void BaseTags::setCache(BaseCache *_cache) { + assert(!cache); cache = _cache; } diff --git a/src/mem/cache/tags/base_set_assoc.cc b/src/mem/cache/tags/base_set_assoc.cc index 637edd557..0d955255a 100644 --- a/src/mem/cache/tags/base_set_assoc.cc +++ b/src/mem/cache/tags/base_set_assoc.cc @@ -76,7 +76,6 @@ BaseSetAssoc::BaseSetAssoc(const Params *p) setShift = floorLog2(blkSize); setMask = numSets - 1; tagShift = setShift + floorLog2(numSets); - warmedUp = false; /** @todo Make warmup percentage a parameter. */ warmupBound = numSets * assoc; diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc index 6526aadb8..6a63da673 100644 --- a/src/mem/cache/tags/fa_lru.cc +++ b/src/mem/cache/tags/fa_lru.cc @@ -55,7 +55,7 @@ using namespace std; FALRU::FALRU(const Params *p) - : BaseTags(p) + : BaseTags(p), cacheBoundaries(nullptr) { if (!isPowerOf2(blkSize)) fatal("cache block size (in bytes) `%d' must be a power of two", @@ -74,7 +74,6 @@ FALRU::FALRU(const Params *p) cacheMask = 0; } - warmedUp = false; warmupBound = size/blkSize; numBlocks = size/blkSize; |