6 files changed, 81 insertions, 15 deletions

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 15a21efa1..451da28e8 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -59,7 +59,7 @@ void
 BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
                                        AddrRangeList &snoop)
 {
-    cache->getAddressRanges(resp, snoop);
+    cache->getAddressRanges(resp, snoop, isCpuSide);
 }
 
 int
@@ -117,10 +117,29 @@ BaseCache::CacheEvent::process()
     if (!pkt)
     {
         if (!cachePort->isCpuSide)
+        {
             pkt = cachePort->cache->getPacket();
-        //Else get coherence req
+            bool success = cachePort->sendTiming(pkt);
+            DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
+                    pkt->getAddr(), success ? "succesful" : "unsuccesful");
+            cachePort->cache->sendResult(pkt, success);
+            if (success && cachePort->cache->doMasterRequest())
+            {
+                //Still more to issue, rerequest in 1 cycle
+                pkt = NULL;
+                this->schedule(curTick+1);
+            }
+        }
+        else
+        {
+            pkt = cachePort->cache->getCoherencePacket();
+            cachePort->sendTiming(pkt);
+        }
+        return;
     }
-    cachePort->sendTiming(pkt);
+    //Know the packet to send, no need to mark in service (must succed)
+    bool success = cachePort->sendTiming(pkt);
+    assert(success);
 }
 
 const char *
@@ -138,7 +157,13 @@ BaseCache::getPort(const std::string &if_name, int idx)
             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
         return cpuSidePort;
     }
-    if (if_name == "functional")
+    else if (if_name == "functional")
+    {
+        if(cpuSidePort == NULL)
+            cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
+        return cpuSidePort;
+    }
+    else if (if_name == "cpu_side")
     {
         if(cpuSidePort == NULL)
             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
@@ -155,6 +180,14 @@ BaseCache::getPort(const std::string &if_name, int idx)
 }
 
 void
+BaseCache::init()
+{
+    if (!cpuSidePort || !memSidePort)
+        panic("Cache not hooked up on both sides\n");
+    cpuSidePort->sendStatusChange(Port::RangeChange);
+}
+
+void
 BaseCache::regStats()
 {
     Request temp_req((Addr) NULL, 4, 0);
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 5370a73c8..0d1bfdfdb 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -143,9 +143,19 @@ class BaseCache : public MemObject
         fatal("No implementation");
     }
 
-    virtual void recvStatusChange(Port::Status status, bool isCpuSide)
+    void recvStatusChange(Port::Status status, bool isCpuSide)
     {
-        fatal("No implementation");
+        if (status == Port::RangeChange)
+        {
+            if (!isCpuSide)
+            {
+                cpuSidePort->sendStatusChange(Port::RangeChange);
+            }
+            else
+            {
+                memSidePort->sendStatusChange(Port::RangeChange);
+            }
+        }
     }
 
     virtual Packet *getPacket()
@@ -153,6 +163,17 @@ class BaseCache : public MemObject
         fatal("No implementation");
     }
 
+    virtual Packet *getCoherencePacket()
+    {
+        fatal("No implementation");
+    }
+
+    virtual void sendResult(Packet* &pkt, bool success)
+    {
+
+        fatal("No implementation");
+    }
+
     /**
      * Bit vector of the blocking reasons for the access path.
      * @sa #BlockedCause
@@ -309,6 +330,8 @@ class BaseCache : public MemObject
         memSidePort = NULL;
     }
 
+    virtual void init();
+
     /**
      * Query block size of a cache.
      * @return  The block size
@@ -508,9 +531,18 @@ class BaseCache : public MemObject
      */
     void rangeChange() {}
 
-    void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
+    void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
     {
-        panic("Unimplimented\n");
+        if (isCpuSide)
+        {
+            AddrRangeList dummy;
+            memSidePort->getPeerAddressRanges(resp, dummy);
+        }
+        else
+        {
+            //This is where snoops get updated
+            return;
+        }
     }
 };
 
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 2e77444a0..ec5b800a8 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -175,7 +175,7 @@ class Cache : public BaseCache
      * @param req The request.
      * @param success True if the request was sent successfully.
      */
-    void sendResult(Packet * &pkt, bool success);
+    virtual void sendResult(Packet * &pkt, bool success);
 
     /**
      * Handles a response (cache line fill/write ack) from the bus.
@@ -202,7 +202,7 @@ class Cache : public BaseCache
      * Selects a coherence message to forward to lower levels of the hierarchy.
      * @return The coherence message to forward.
      */
-    Packet * getCoherenceReq();
+    virtual Packet * getCoherencePacket();
 
     /**
      * Snoops bus transactions to maintain coherence.
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index aae5cbf01..a447ae3d5 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -350,7 +350,7 @@ Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 
 template<class TagStore, class Buffering, class Coherence>
 Packet *
-Cache<TagStore,Buffering,Coherence>::getCoherenceReq()
+Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 {
     return coherence->getPacket();
 }
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index da0448ad3..4a3dc1062 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -352,7 +352,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
 MSHR*
 MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
 {
-    MSHR* mshr = mq.allocate(pkt, size);
+    MSHR* mshr = mq.allocate(pkt, blkSize);
     mshr->order = order++;
     if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
         // Mark this as a cache line fill
@@ -372,7 +372,7 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
 MSHR*
 MissQueue::allocateWrite(Packet * &pkt, int size, Tick time)
 {
-    MSHR* mshr = wb.allocate(pkt,pkt->getSize());
+    MSHR* mshr = wb.allocate(pkt,blkSize);
     mshr->order = order++;
 
 //REMOVING COMPRESSION FOR NOW
@@ -446,11 +446,11 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
         /**
          * @todo Add write merging here.
          */
-        mshr = allocateWrite(pkt, pkt->getSize(), time);
+        mshr = allocateWrite(pkt, blkSize, time);
         return;
     }
 
-    mshr = allocateMiss(pkt, size, time);
+    mshr = allocateMiss(pkt, blkSize, time);
 }
 
 MSHR*
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 1a85d3018..db2f40c56 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -57,6 +57,7 @@ void
 MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
                Packet * &target)
 {
+    addr = _addr;
     if (target)
     {
         //Have a request, just use it