diff options
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/base.hh | 22 | ||||
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 8 |
2 files changed, 4 insertions, 26 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 79280f377..795347a0d 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -134,17 +134,6 @@ class BaseCache : public MemObject queue.schedSendEvent(time); } - /** - * Schedule the transmissions of a response packet at a given - * point in time. - * - * @param pkt response packet - * @param when time to send the response - */ - void respond(PacketPtr pkt, Tick time) { - queue.schedSendTiming(pkt, time, true); - } - protected: CacheMasterPort(const std::string &_name, BaseCache *_cache, @@ -179,17 +168,6 @@ class BaseCache : public MemObject /** Return to normal operation and accept new requests. */ void clearBlocked(); - /** - * Schedule the transmissions of a response packet at a given - * point in time. - * - * @param pkt response packet - * @param when time to send the response - */ - void respond(PacketPtr pkt, Tick time) { - queue.schedSendTiming(pkt, time); - } - protected: CacheSlavePort(const std::string &_name, BaseCache *_cache, diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 8e6c39644..4d8adbd90 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -407,7 +407,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt) rec->restore(pkt, this); delete rec; - memSidePort->respond(pkt, time); + memSidePort->schedTimingSnoopResp(pkt, time); return true; } @@ -500,7 +500,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt) if (needsResponse) { pkt->makeTimingResponse(); - cpuSidePort->respond(pkt, curTick()+lat); + cpuSidePort->schedTimingResp(pkt, curTick()+lat); } else { /// @todo nominally we should just delete the packet here, /// however, until 4-phase stuff we can't because sending @@ -933,7 +933,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt) // isInvalidate() set otherwise. target->pkt->cmd = MemCmd::ReadRespWithInvalidate; } - cpuSidePort->respond(target->pkt, completion_time); + cpuSidePort->schedTimingResp(target->pkt, completion_time); break; case MSHR::Target::FromPrefetcher: @@ -1166,7 +1166,7 @@ doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, // invalidate it. pkt->cmd = MemCmd::ReadRespWithInvalidate; } - memSidePort->respond(pkt, curTick() + hitLatency); + memSidePort->schedTimingSnoopResp(pkt, curTick() + hitLatency); } template<class TagStore> |