diff options
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 4 | ||||
| -rw-r--r-- | src/mem/cache/miss/blocking_buffer.cc | 2 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/tagged_prefetcher_impl.hh | 1 |
3 files changed, 2 insertions, 5 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index a447ae3d5..56e7a4d58 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -53,8 +53,6 @@ #include "sim/sim_events.hh" // for SimExitEvent -using namespace std; - template<class TagStore, class Buffering, class Coherence> bool Cache<TagStore,Buffering,Coherence>:: @@ -501,7 +499,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update) MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid()); // There can be many matching outstanding writes. - vector<MSHR*> writes; + std::vector<MSHR*> writes; missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes); if (!update) { diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc index 10d53b109..2f61e8a54 100644 --- a/src/mem/cache/miss/blocking_buffer.cc +++ b/src/mem/cache/miss/blocking_buffer.cc @@ -40,8 +40,6 @@ #include "sim/eventq.hh" // for Event declaration. #include "mem/request.hh" -using namespace TheISA; - /** * @todo Move writebacks into shared BaseBuffer class. */ diff --git a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh index db5c94820..e554b3cec 100644 --- a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh +++ b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh @@ -33,6 +33,7 @@ * Describes a tagged prefetcher based on template policies. */ +#include "arch/isa_traits.hh" #include "mem/cache/prefetch/tagged_prefetcher.hh" template <class TagStore, class Buffering> |