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-rw-r--r--src/mem/cache/base.cc8
-rw-r--r--src/mem/cache/base.hh6
2 files changed, 8 insertions, 6 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index c95999f3e..a88749627 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -118,8 +118,8 @@ BaseCache::init()
cpuSidePort->sendRangeChange();
}
-MasterPort &
-BaseCache::getMasterPort(const std::string &if_name, int idx)
+BaseMasterPort &
+BaseCache::getMasterPort(const std::string &if_name, PortID idx)
{
if (if_name == "mem_side") {
return *memSidePort;
@@ -128,8 +128,8 @@ BaseCache::getMasterPort(const std::string &if_name, int idx)
}
}
-SlavePort &
-BaseCache::getSlavePort(const std::string &if_name, int idx)
+BaseSlavePort &
+BaseCache::getSlavePort(const std::string &if_name, PortID idx)
{
if (if_name == "cpu_side") {
return *cpuSidePort;
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 2e31836c0..42ade9b0b 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -430,8 +430,10 @@ class BaseCache : public MemObject
virtual void init();
- virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
- virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1);
+ virtual BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID);
+ virtual BaseSlavePort &getSlavePort(const std::string &if_name,
+ PortID idx = InvalidPortID);
/**
* Query block size of a cache.