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-rw-r--r--src/mem/cache/base.cc2
-rw-r--r--src/mem/cache/base.hh4
-rw-r--r--src/mem/cache/blk.hh2
-rw-r--r--src/mem/cache/cache_impl.hh18
-rw-r--r--src/mem/cache/mshr.cc4
-rw-r--r--src/mem/cache/mshr.hh2
-rw-r--r--src/mem/cache/mshr_queue.hh2
-rw-r--r--src/mem/cache/tags/fa_lru.cc2
-rw-r--r--src/mem/cache/tags/iic.cc6
-rw-r--r--src/mem/cache/tags/lru.cc8
10 files changed, 25 insertions, 25 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 70bc51cda..9166e1a09 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -124,7 +124,7 @@ BaseCache::CachePort::clearBlocked()
mustSendRetry = false;
SendRetryEvent *ev = new SendRetryEvent(this, true);
// @TODO: need to find a better time (next bus cycle?)
- schedule(ev, curTick + 1);
+ schedule(ev, curTick() + 1);
}
}
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 867d77121..e8a644296 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -434,7 +434,7 @@ class BaseCache : public MemObject
uint8_t flag = 1 << cause;
if (blocked == 0) {
blocked_causes[cause]++;
- blockedCycle = curTick;
+ blockedCycle = curTick();
cpuSidePort->setBlocked();
}
blocked |= flag;
@@ -454,7 +454,7 @@ class BaseCache : public MemObject
blocked &= ~flag;
DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
if (blocked == 0) {
- blocked_cycles[cause] += curTick - blockedCycle;
+ blocked_cycles[cause] += curTick() - blockedCycle;
cpuSidePort->clearBlocked();
}
}
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index bf78a2268..6be09597c 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -89,7 +89,7 @@ class CacheBlk
/** The current status of this block. @sa CacheBlockStatusBits */
State status;
- /** Which curTick will this block be accessable */
+ /** Which curTick() will this block be accessable */
Tick whenReady;
/**
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index c5b7ca065..e4e4a3c92 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -412,7 +412,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
// MemDebug::cacheAccess(pkt);
// we charge hitLatency for doing just about anything here
- Tick time = curTick + hitLatency;
+ Tick time = curTick() + hitLatency;
if (pkt->isResponse()) {
// must be cache-to-cache response from upper to lower level
@@ -504,7 +504,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
if (satisfied) {
if (needsResponse) {
pkt->makeTimingResponse();
- cpuSidePort->respond(pkt, curTick+lat);
+ cpuSidePort->respond(pkt, curTick()+lat);
} else {
delete pkt;
}
@@ -532,7 +532,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
noTargetMSHR = mshr;
setBlocked(Blocked_NoTargets);
// need to be careful with this... if this mshr isn't
- // ready yet (i.e. time > curTick_, we don't want to
+ // ready yet (i.e. time > curTick()_, we don't want to
// move it ahead of mshrs that are ready
// mshrQueue.moveToFront(mshr);
}
@@ -816,7 +816,7 @@ template<class TagStore>
void
Cache<TagStore>::handleResponse(PacketPtr pkt)
{
- Tick time = curTick + hitLatency;
+ Tick time = curTick() + hitLatency;
MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
bool is_error = pkt->isError();
@@ -848,7 +848,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
MSHR::Target *initial_tgt = mshr->getTarget();
BlkType *blk = tags->findBlock(pkt->getAddr());
int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
- Tick miss_latency = curTick - initial_tgt->recvTime;
+ Tick miss_latency = curTick() - initial_tgt->recvTime;
PacketList writebacks;
if (pkt->req->isUncacheable()) {
@@ -1159,7 +1159,7 @@ doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
// invalidate it.
pkt->cmd = MemCmd::ReadRespWithInvalidate;
}
- memSidePort->respond(pkt, curTick + hitLatency);
+ memSidePort->respond(pkt, curTick() + hitLatency);
}
template<class TagStore>
@@ -1430,7 +1430,7 @@ Cache<TagStore>::getNextMSHR()
// (hwpf_mshr_misses)
mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
// Don't request bus, since we already have it
- return allocateMissBuffer(pkt, curTick, false);
+ return allocateMissBuffer(pkt, curTick(), false);
}
}
}
@@ -1461,7 +1461,7 @@ Cache<TagStore>::getTimingPacket()
pkt = new Packet(tgt_pkt);
pkt->cmd = MemCmd::UpgradeFailResp;
pkt->senderState = mshr;
- pkt->firstWordTime = pkt->finishTime = curTick;
+ pkt->firstWordTime = pkt->finishTime = curTick();
handleResponse(pkt);
return NULL;
} else if (mshr->isForwardNoResponse()) {
@@ -1679,7 +1679,7 @@ Cache<TagStore>::MemSidePort::sendPacket()
// @TODO: need to facotr in prefetch requests here somehow
if (nextReady != MaxTick) {
DPRINTF(CachePort, "more packets to send @ %d\n", nextReady);
- schedule(sendEvent, std::max(nextReady, curTick + 1));
+ schedule(sendEvent, std::max(nextReady, curTick() + 1));
} else {
// no more to send right now: if we're draining, we may be done
if (drainEvent && !sendEvent->scheduled()) {
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 54977346f..292c11c6b 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -333,7 +333,7 @@ MSHR::handleSnoop(PacketPtr pkt, Counter _order)
// Actual target device (typ. PhysicalMemory) will delete the
// packet on reception, so we need to save a copy here.
PacketPtr cp_pkt = new Packet(pkt, true);
- targets->add(cp_pkt, curTick, _order, Target::FromSnoop,
+ targets->add(cp_pkt, curTick(), _order, Target::FromSnoop,
downstreamPending && targets->needsExclusive);
++ntargets;
@@ -378,7 +378,7 @@ MSHR::promoteDeferredTargets()
deferredTargets->resetFlags();
order = targets->front().order;
- readyTime = std::max(curTick, targets->front().readyTime);
+ readyTime = std::max(curTick(), targets->front().readyTime);
return true;
}
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 9b55e70ef..7920ad717 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -72,7 +72,7 @@ class MSHR : public Packet::SenderState, public Printable
Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
Source _source, bool _markedPending)
- : recvTime(curTick), readyTime(_readyTime), order(_order),
+ : recvTime(curTick()), readyTime(_readyTime), order(_order),
pkt(_pkt), source(_source), markedPending(_markedPending)
{}
};
diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index d8c495679..5a8739fc7 100644
--- a/src/mem/cache/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
@@ -199,7 +199,7 @@ class MSHRQueue
*/
MSHR *getNextMSHR() const
{
- if (readyList.empty() || readyList.front()->readyTime > curTick) {
+ if (readyList.empty() || readyList.front()->readyTime > curTick()) {
return NULL;
}
return readyList.front();
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index 4d1c2175f..873883c1b 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -220,7 +220,7 @@ FALRU::findVictim(Addr addr, PacketList &writebacks)
blk->isTouched = true;
if (!warmedUp && tagsInUse.value() >= warmupBound) {
warmedUp = true;
- warmupCycle = curTick;
+ warmupCycle = curTick();
}
}
//assert(check());
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 1315a17ee..743c6894f 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -257,8 +257,8 @@ IIC::accessBlock(Addr addr, int &lat, int context_src)
hitDepthTotal += sets[set].depth;
tag_ptr->status |= BlkReferenced;
lat = set_lat;
- if (tag_ptr->whenReady > curTick && tag_ptr->whenReady - curTick > set_lat) {
- lat = tag_ptr->whenReady - curTick;
+ if (tag_ptr->whenReady > curTick() && tag_ptr->whenReady - curTick() > set_lat) {
+ lat = tag_ptr->whenReady - curTick();
}
tag_ptr->refCount += 1;
@@ -437,7 +437,7 @@ IIC::getFreeTag(int set, PacketList & writebacks)
tagsInUse++;
if (!warmedUp && tagsInUse.value() >= warmupBound) {
warmedUp = true;
- warmupCycle = curTick;
+ warmupCycle = curTick();
}
return tag_ptr;
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 8a8b0d0d6..25e98d293 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -126,9 +126,9 @@ LRU::accessBlock(Addr addr, int &lat, int context_src)
sets[set].moveToHead(blk);
DPRINTF(CacheRepl, "set %x: moving blk %x to MRU\n",
set, regenerateBlkAddr(tag, set));
- if (blk->whenReady > curTick
- && blk->whenReady - curTick > hitLatency) {
- lat = blk->whenReady - curTick;
+ if (blk->whenReady > curTick()
+ && blk->whenReady - curTick() > hitLatency) {
+ lat = blk->whenReady - curTick();
}
blk->refCount += 1;
}
@@ -180,7 +180,7 @@ LRU::insertBlock(Addr addr, BlkType *blk, int context_src)
blk->isTouched = true;
if (!warmedUp && tagsInUse.value() >= warmupBound) {
warmedUp = true;
- warmupCycle = curTick;
+ warmupCycle = curTick();
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 13:08:39 +0000