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-rw-r--r--src/mem/cache/cache_impl.hh1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 7bab3012b..3b56c0a2e 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -823,7 +823,6 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
}
if (mshr->promoteDeferredTargets()) {
- assert(mshr->needsExclusive() && !blk->isWritable());
// avoid later read getting stale data while write miss is
// outstanding.. see comment in timingAccess()
blk->status &= ~BlkReadable;