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-rw-r--r--src/mem/cache/SConscript3
-rw-r--r--src/mem/cache/prefetch/SConscript3
-rw-r--r--src/mem/cache/tags/SConscript3
3 files changed, 9 insertions, 0 deletions
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index 3b8bdb0c8..781521d3f 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -30,6 +30,9 @@
Import('*')
+if env['TARGET_ISA'] == 'no':
+ Return()
+
SimObject('BaseCache.py')
Source('base.cc')
diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript
index 7314b5ccf..9d05a8ee4 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -30,6 +30,9 @@
Import('*')
+if env['TARGET_ISA'] == 'no':
+ Return()
+
Source('base.cc')
Source('ghb.cc')
Source('stride.cc')
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 37ed5dc85..d640a9f13 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -30,6 +30,9 @@
Import('*')
+if env['TARGET_ISA'] == 'no':
+ Return()
+
Source('base.cc')
Source('fa_lru.cc')
Source('iic.cc')