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-rw-r--r--src/mem/cache/base_cache.hh6
-rw-r--r--src/mem/cache/cache.hh20
-rw-r--r--src/mem/cache/coherence/coherence_protocol.hh4
-rw-r--r--src/mem/cache/coherence/simple_coherence.hh4
-rw-r--r--src/mem/cache/coherence/uni_coherence.hh4
-rw-r--r--src/mem/cache/miss/blocking_buffer.hh34
-rw-r--r--src/mem/cache/miss/miss_queue.hh42
-rw-r--r--src/mem/cache/miss/mshr.hh22
-rw-r--r--src/mem/cache/miss/mshr_queue.hh34
-rw-r--r--src/mem/cache/tags/fa_lru.hh6
-rw-r--r--src/mem/cache/tags/iic.hh10
-rw-r--r--src/mem/cache/tags/lru.hh6
-rw-r--r--src/mem/cache/tags/split.hh14
-rw-r--r--src/mem/cache/tags/split_blk.hh2
-rw-r--r--src/mem/cache/tags/split_lifo.hh6
-rw-r--r--src/mem/cache/tags/split_lru.hh6
16 files changed, 110 insertions, 110 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 0d1bfdfdb..7f0cb56f2 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -488,7 +488,7 @@ class BaseCache : public MemObject
/**
* Send a response to the slave interface.
- * @param req The request being responded to.
+ * @param pkt The request being responded to.
* @param time The time the response is ready.
*/
void respond(Packet *pkt, Tick time)
@@ -501,7 +501,7 @@ class BaseCache : public MemObject
/**
* Send a reponse to the slave interface and calculate miss latency.
- * @param req The request to respond to.
+ * @param pkt The request to respond to.
* @param time The time the response is ready.
*/
void respondToMiss(Packet *pkt, Tick time)
@@ -517,7 +517,7 @@ class BaseCache : public MemObject
/**
* Suppliess the data if cache to cache transfers are enabled.
- * @param req The bus transaction to fulfill.
+ * @param pkt The bus transaction to fulfill.
*/
void respondToSnoop(Packet *pkt)
{
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index ec5b800a8..a26d91709 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -159,7 +159,7 @@ class Cache : public BaseCache
/**
* Performs the access specified by the request.
- * @param req The request to perform.
+ * @param pkt The request to perform.
* @return The result of the access.
*/
bool access(Packet * &pkt);
@@ -172,26 +172,26 @@ class Cache : public BaseCache
/**
* Was the request was sent successfully?
- * @param req The request.
+ * @param pkt The request.
* @param success True if the request was sent successfully.
*/
virtual void sendResult(Packet * &pkt, bool success);
/**
* Handles a response (cache line fill/write ack) from the bus.
- * @param req The request being responded to.
+ * @param pkt The request being responded to.
*/
void handleResponse(Packet * &pkt);
/**
* Start handling a copy transaction.
- * @param req The copy request to perform.
+ * @param pkt The copy request to perform.
*/
void startCopy(Packet * &pkt);
/**
* Handle a delayed copy transaction.
- * @param req The delayed copy request to continue.
+ * @param pkt The delayed copy request to continue.
* @param addr The address being responded to.
* @param blk The block of the current response.
* @param mshr The mshr being handled.
@@ -206,7 +206,7 @@ class Cache : public BaseCache
/**
* Snoops bus transactions to maintain coherence.
- * @param req The current bus transaction.
+ * @param pkt The current bus transaction.
*/
void snoop(Packet * &pkt);
@@ -221,9 +221,9 @@ class Cache : public BaseCache
void invalidateBlk(Addr addr, int asid);
/**
- * Aquash all requests associated with specified thread.
+ * Squash all requests associated with specified thread.
* intended for use by I-cache.
- * @param req->getThreadNum()ber The thread to squash.
+ * @param threadNum The thread to squash.
*/
void squash(int threadNum)
{
@@ -246,7 +246,7 @@ class Cache : public BaseCache
* time of completion. This function can either update the hierarchy state
* or just perform the access wherever the data is found depending on the
* state of the update flag.
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
@@ -257,7 +257,7 @@ class Cache : public BaseCache
* Snoop for the provided request in the cache and return the estimated
* time of completion.
* @todo Can a snoop probe not change state?
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
diff --git a/src/mem/cache/coherence/coherence_protocol.hh b/src/mem/cache/coherence/coherence_protocol.hh
index 21351ace4..b5d7d80aa 100644
--- a/src/mem/cache/coherence/coherence_protocol.hh
+++ b/src/mem/cache/coherence/coherence_protocol.hh
@@ -85,7 +85,7 @@ class CoherenceProtocol : public SimObject
/**
* Return the proper state given the current state and the bus response.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param oldState The current block state.
* @return The new state.
*/
@@ -95,7 +95,7 @@ class CoherenceProtocol : public SimObject
/**
* Handle snooped bus requests.
* @param cache The cache that snooped the request.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state The new coherence state of the block.
diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh
index ca9d18beb..71d8f36f4 100644
--- a/src/mem/cache/coherence/simple_coherence.hh
+++ b/src/mem/cache/coherence/simple_coherence.hh
@@ -96,7 +96,7 @@ class SimpleCoherence
/**
* Return the proper state given the current state and the bus response.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param current The current block state.
* @return The new state.
*/
@@ -107,7 +107,7 @@ class SimpleCoherence
/**
* Handle snooped bus requests.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state Return the new state for the block.
diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh
index 764bf6276..27b6c7fb5 100644
--- a/src/mem/cache/coherence/uni_coherence.hh
+++ b/src/mem/cache/coherence/uni_coherence.hh
@@ -88,7 +88,7 @@ class UniCoherence
/**
* Just return readable and writeable.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param current The current block state.
* @return The new state.
*/
@@ -116,7 +116,7 @@ class UniCoherence
/**
* Handle snooped bus requests.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state The new coherence state of the block.
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh
index 39a06a377..a6261f62c 100644
--- a/src/mem/cache/miss/blocking_buffer.hh
+++ b/src/mem/cache/miss/blocking_buffer.hh
@@ -107,7 +107,7 @@ public:
/**
* Handle a cache miss properly. Requests the bus and marks the cache as
* blocked.
- * @param req The request that missed in the cache.
+ * @param pkt The request that missed in the cache.
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
@@ -128,43 +128,43 @@ public:
}
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Selects a outstanding pktuest to service.
+ * @return The pktuest to service, NULL if none found.
*/
Packet * getPacket();
/**
* Set the command to the given bus command.
- * @param req The request to update.
+ * @param pkt The request to update.
* @param cmd The bus command to use.
*/
void setBusCmd(Packet * &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
- * @param req The request to reset.
+ * @param pkt The request to reset.
*/
void restoreOrigCmd(Packet * &pkt);
/**
- * Marks a request as in service (sent on the bus). This can have side
+ * Marks a pktuest as in service (sent on the bus). This can have side
* effect since storage for no response commands is deallocated once they
* are successfully sent.
- * @param req The request that was sent on the bus.
+ * @param pkt The request that was sent on the bus.
*/
void markInService(Packet * &pkt);
/**
- * Frees the resources of the request and unblock the cache.
- * @param req The request that has been satisfied.
- * @param time The time when the request is satisfied.
+ * Frees the resources of the pktuest and unblock the cache.
+ * @param pkt The request that has been satisfied.
+ * @param time The time when the pktuest is satisfied.
*/
void handleResponse(Packet * &pkt, Tick time);
/**
- * Removes all outstanding requests for a given thread number. If a request
+ * Removes all outstanding pktuests for a given thread number. If a request
* has been sent to the bus, this function removes all of its targets.
- * @param req->getThreadNum()ber The thread number of the requests to squash.
+ * @param threadNum The thread number of the requests to squash.
*/
void squash(int threadNum);
@@ -220,14 +220,14 @@ public:
int size, uint8_t *data, bool compressed);
/**
- * Perform a writeback request.
- * @param req The writeback request.
+ * Perform a writeback pktuest.
+ * @param pkt The writeback request.
*/
void doWriteback(Packet * &pkt);
/**
- * Returns true if there are outstanding requests.
- * @return True if there are outstanding requests.
+ * Returns true if there are outstanding pktuests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending()
{
@@ -237,7 +237,7 @@ public:
/**
* Add a target to the given MSHR. This assumes it is in the miss queue.
* @param mshr The mshr to add a target to.
- * @param req The target to add.
+ * @param pkt The target to add.
*/
void addTarget(MSHR *mshr, Packet * &pkt)
{
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index b88b7038c..c558df956 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -77,7 +77,7 @@ class MissQueue
/** The block size of the parent cache. */
int blkSize;
- /** Increasing order number assigned to each incoming request. */
+ /** Increasing order number assigned to each incoming pktuest. */
uint64_t order;
bool prefetchMiss;
@@ -164,7 +164,7 @@ class MissQueue
/**
* Allocate a new MSHR to handle the provided miss.
- * @param req The miss to buffer.
+ * @param pkt The miss to buffer.
* @param size The number of bytes to fetch.
* @param time The time the miss occurs.
* @return A pointer to the new MSHR.
@@ -173,7 +173,7 @@ class MissQueue
/**
* Allocate a new WriteBuffer to handle the provided write.
- * @param req The write to handle.
+ * @param pkt The write to handle.
* @param size The number of bytes to write.
* @param time The time the write occurs.
* @return A pointer to the new write buffer.
@@ -212,9 +212,9 @@ class MissQueue
void setPrefetcher(BasePrefetcher *_prefetcher);
/**
- * Handle a cache miss properly. Either allocate an MSHR for the request,
+ * Handle a cache miss properly. Either allocate an MSHR for the pktuest,
* or forward it through the write buffer.
- * @param req The request that missed in the cache.
+ * @param pkt The request that missed in the cache.
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
@@ -232,43 +232,43 @@ class MissQueue
Packet * &target);
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Selects a outstanding pktuest to service.
+ * @return The pktuest to service, NULL if none found.
*/
Packet * getPacket();
/**
* Set the command to the given bus command.
- * @param req The request to update.
+ * @param pkt The request to update.
* @param cmd The bus command to use.
*/
void setBusCmd(Packet * &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
- * @param req The request to reset.
+ * @param pkt The request to reset.
*/
void restoreOrigCmd(Packet * &pkt);
/**
- * Marks a request as in service (sent on the bus). This can have side
+ * Marks a pktuest as in service (sent on the bus). This can have side
* effect since storage for no response commands is deallocated once they
* are successfully sent.
- * @param req The request that was sent on the bus.
+ * @param pkt The request that was sent on the bus.
*/
void markInService(Packet * &pkt);
/**
- * Collect statistics and free resources of a satisfied request.
- * @param req The request that has been satisfied.
- * @param time The time when the request is satisfied.
+ * Collect statistics and free resources of a satisfied pktuest.
+ * @param pkt The request that has been satisfied.
+ * @param time The time when the pktuest is satisfied.
*/
void handleResponse(Packet * &pkt, Tick time);
/**
- * Removes all outstanding requests for a given thread number. If a request
+ * Removes all outstanding pktuests for a given thread number. If a request
* has been sent to the bus, this function removes all of its targets.
- * @param req->getThreadNum()ber The thread number of the requests to squash.
+ * @param threadNum The thread number of the requests to squash.
*/
void squash(int threadNum);
@@ -313,21 +313,21 @@ class MissQueue
int size, uint8_t *data, bool compressed);
/**
- * Perform the given writeback request.
- * @param req The writeback request.
+ * Perform the given writeback pktuest.
+ * @param pkt The writeback request.
*/
void doWriteback(Packet * &pkt);
/**
- * Returns true if there are outstanding requests.
- * @return True if there are outstanding requests.
+ * Returns true if there are outstanding pktuests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending();
/**
* Add a target to the given MSHR. This assumes it is in the miss queue.
* @param mshr The mshr to add a target to.
- * @param req The target to add.
+ * @param pkt The target to add.
*/
void addTarget(MSHR *mshr, Packet * &pkt)
{
diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh
index 167aa26cd..ad2865973 100644
--- a/src/mem/cache/miss/mshr.hh
+++ b/src/mem/cache/miss/mshr.hh
@@ -44,7 +44,7 @@ class MSHR;
/**
* Miss Status and handling Register. This class keeps all the information
- * needed to handle a cache miss including a list of target requests.
+ * needed to handle a cache miss including a list of target pktuests.
*/
class MSHR {
public:
@@ -63,15 +63,15 @@ class MSHR {
Addr addr;
/** Adress space id of the miss. */
short asid;
- /** True if the request has been sent to the bus. */
+ /** True if the pktuest has been sent to the bus. */
bool inService;
/** Thread number of the miss. */
int threadNum;
- /** The request that is forwarded to the next level of the hierarchy. */
+ /** The pktuest that is forwarded to the next level of the hierarchy. */
Packet * pkt;
/** The number of currently allocated targets. */
short ntargets;
- /** The original requesting command. */
+ /** The original pktuesting command. */
Packet::Command originalCmd;
/** Order number of assigned by the miss queue. */
uint64_t order;
@@ -88,24 +88,24 @@ class MSHR {
Iterator allocIter;
private:
- /** List of all requests that match the address */
+ /** List of all pktuests that match the address */
TargetList targets;
public:
/**
* Allocate a miss to this MSHR.
- * @param cmd The requesting command.
+ * @param cmd The pktuesting command.
* @param addr The address of the miss.
* @param asid The address space id of the miss.
- * @param size The number of bytes to request.
- * @param req The original miss.
+ * @param size The number of bytes to pktuest.
+ * @param pkt The original miss.
*/
void allocate(Packet::Command cmd, Addr addr, int asid, int size,
Packet * &pkt);
/**
- * Allocate this MSHR as a buffer for the given request.
- * @param target The memory request to buffer.
+ * Allocate this MSHR as a buffer for the given pktuest.
+ * @param target The memory pktuest to buffer.
*/
void allocateAsBuffer(Packet * &target);
@@ -115,7 +115,7 @@ public:
void deallocate();
/**
- * Add a request to the list of targets.
+ * Add a pktuest to the list of targets.
* @param target The target.
*/
void allocateTarget(Packet * &target);
diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh
index a67f1b9a6..02b6a026d 100644
--- a/src/mem/cache/miss/mshr_queue.hh
+++ b/src/mem/cache/miss/mshr_queue.hh
@@ -39,7 +39,7 @@
#include "mem/cache/miss/mshr.hh"
/**
- * A Class for maintaining a list of pending and allocated memory requests.
+ * A Class for maintaining a list of pending and allocated memory pktuests.
*/
class MSHRQueue {
private:
@@ -55,7 +55,7 @@ class MSHRQueue {
// Parameters
/**
* The total number of MSHRs in this queue. This number is set as the
- * number of MSHRs requested plus (numReserve - 1). This allows for
+ * number of MSHRs pktuested plus (numReserve - 1). This allows for
* the same number of effective MSHRs while still maintaining the reserve.
*/
const int numMSHRs;
@@ -103,16 +103,16 @@ class MSHRQueue {
bool findMatches(Addr addr, int asid, std::vector<MSHR*>& matches) const;
/**
- * Find any pending requests that overlap the given request.
- * @param req The request to find.
+ * Find any pending pktuests that overlap the given request.
+ * @param pkt The request to find.
* @return A pointer to the earliest matching MSHR.
*/
MSHR* findPending(Packet * &pkt) const;
/**
- * Allocates a new MSHR for the request and size. This places the request
+ * Allocates a new MSHR for the pktuest and size. This places the request
* as the first target in the MSHR.
- * @param req The request to handle.
+ * @param pkt The request to handle.
* @param size The number in bytes to fetch from memory.
* @return The a pointer to the MSHR allocated.
*
@@ -121,12 +121,12 @@ class MSHRQueue {
MSHR* allocate(Packet * &pkt, int size = 0);
/**
- * Allocate a read request for the given address, and places the given
+ * Allocate a read pktuest for the given address, and places the given
* target on the target list.
* @param addr The address to fetch.
* @param asid The address space for the fetch.
- * @param size The number of bytes to request.
- * @param target The first target for the request.
+ * @param size The number of bytes to pktuest.
+ * @param target The first target for the pktuest.
* @return Pointer to the new MSHR.
*/
MSHR* allocateFetch(Addr addr, int asid, int size, Packet * &target);
@@ -135,7 +135,7 @@ class MSHRQueue {
* Allocate a target list for the given address.
* @param addr The address to fetch.
* @param asid The address space for the fetch.
- * @param size The number of bytes to request.
+ * @param size The number of bytes to pktuest.
* @return Pointer to the new MSHR.
*/
MSHR* allocateTargetList(Addr addr, int asid, int size);
@@ -151,7 +151,7 @@ class MSHRQueue {
* Allocates a target to the given MSHR. Used to keep track of the number
* of outstanding targets.
* @param mshr The MSHR to allocate the target to.
- * @param req The target request.
+ * @param pkt The target request.
*/
void allocateTarget(MSHR* mshr, Packet * &pkt)
{
@@ -181,22 +181,22 @@ class MSHRQueue {
void markInService(MSHR* mshr);
/**
- * Mark an in service mshr as pending, used to resend a request.
+ * Mark an in service mshr as pending, used to resend a pktuest.
* @param mshr The MSHR to resend.
* @param cmd The command to resend.
*/
void markPending(MSHR* mshr, Packet::Command cmd);
/**
- * Squash outstanding requests with the given thread number. If a request
+ * Squash outstanding pktuests with the given thread number. If a request
* is in service, just squashes the targets.
- * @param req->getThreadNum()ber The thread to squash.
+ * @param threadNum The thread to squash.
*/
void squash(int threadNum);
/**
* Returns true if the pending list is not empty.
- * @return True if there are outstanding requests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending() const
{
@@ -213,8 +213,8 @@ class MSHRQueue {
}
/**
- * Returns the request at the head of the pendingList.
- * @return The next request to service.
+ * Returns the pktuest at the head of the pendingList.
+ * @return The next pktuest to service.
*/
Packet * getReq() const
{
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 566e36c27..444954917 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -193,7 +193,7 @@ public:
/**
* Find the block in the cache and update the replacement data. Returns
* the access latency and the in cache flags as a side effect
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The latency of the access.
* @param inCache The FALRUBlk::inCache flags.
* @return Pointer to the cache block.
@@ -210,7 +210,7 @@ public:
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -328,7 +328,7 @@ public:
* @param source The block aligned source address.
* @param dest The block aligned destination adddress.
* @param asid The address space ID.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks)
{
diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh
index 6628f7e7a..514d16bdd 100644
--- a/src/mem/cache/tags/iic.hh
+++ b/src/mem/cache/tags/iic.hh
@@ -454,7 +454,7 @@ class IIC : public BaseTags
/**
* Find the block and update the replacement data. This call also returns
* the access latency as a side effect.
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The access latency.
* @return A pointer to the block found, if any.
*/
@@ -470,7 +470,7 @@ class IIC : public BaseTags
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -502,14 +502,14 @@ class IIC : public BaseTags
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
/**
* If a block is currently marked copy on write, copy it before writing.
- * @param req The write request.
- * @param writebacks List for any generated writeback requests.
+ * @param pkt The write request.
+ * @param writebacks List for any generated writeback pktuests.
*/
void fixCopy(Packet * &pkt, PacketList &writebacks);
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index 437244660..8f0f3ae27 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -170,7 +170,7 @@ public:
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The request whose block to find.
+ * @param pkt The request whose block to find.
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
@@ -196,7 +196,7 @@ public:
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -307,7 +307,7 @@ public:
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
diff --git a/src/mem/cache/tags/split.hh b/src/mem/cache/tags/split.hh
index 5e0340269..25180a02b 100644
--- a/src/mem/cache/tags/split.hh
+++ b/src/mem/cache/tags/split.hh
@@ -71,13 +71,13 @@ class Split : public BaseTags
Addr blkMask;
- /** Number of NIC requests that hit in the NIC partition */
+ /** Number of NIC pktuests that hit in the NIC partition */
Stats::Scalar<> NR_NP_hits;
- /** Number of NIC requests that hit in the CPU partition */
+ /** Number of NIC pktuests that hit in the CPU partition */
Stats::Scalar<> NR_CP_hits;
- /** Number of CPU requests that hit in the NIC partition */
+ /** Number of CPU pktuests that hit in the NIC partition */
Stats::Scalar<> CR_NP_hits;
- /** Number of CPU requests that hit in the CPU partition */
+ /** Number of CPU pktuests that hit in the CPU partition */
Stats::Scalar<> CR_CP_hits;
/** The number of nic replacements (i.e. misses) */
Stats::Scalar<> nic_repl;
@@ -203,7 +203,7 @@ class Split : public BaseTags
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The memory request whose block to find
+ * @param pkt The memory request whose block to find
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
@@ -219,7 +219,7 @@ class Split : public BaseTags
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -315,7 +315,7 @@ class Split : public BaseTags
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
diff --git a/src/mem/cache/tags/split_blk.hh b/src/mem/cache/tags/split_blk.hh
index f38516180..64d903579 100644
--- a/src/mem/cache/tags/split_blk.hh
+++ b/src/mem/cache/tags/split_blk.hh
@@ -47,7 +47,7 @@ class SplitBlk : public CacheBlk {
bool isTouched;
/** Has this block been used after being brought in? (for LIFO partition) */
bool isUsed;
- /** is this blk a NIC block? (i.e. requested by the NIC) */
+ /** is this blk a NIC block? (i.e. pktuested by the NIC) */
bool isNIC;
/** timestamp of the arrival of this block into the cache */
Tick ts;
diff --git a/src/mem/cache/tags/split_lifo.hh b/src/mem/cache/tags/split_lifo.hh
index dfcaa0b67..52956b192 100644
--- a/src/mem/cache/tags/split_lifo.hh
+++ b/src/mem/cache/tags/split_lifo.hh
@@ -203,7 +203,7 @@ public:
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
@@ -219,7 +219,7 @@ public:
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -330,7 +330,7 @@ public:
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
diff --git a/src/mem/cache/tags/split_lru.hh b/src/mem/cache/tags/split_lru.hh
index 03886b1d8..6d370c5dd 100644
--- a/src/mem/cache/tags/split_lru.hh
+++ b/src/mem/cache/tags/split_lru.hh
@@ -186,7 +186,7 @@ public:
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The req whose block to find.
+ * @param pkt The req whose block to find.
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
@@ -202,7 +202,7 @@ public:
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -313,7 +313,7 @@ public:
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 14:19:24 +0000