diff options
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/base.cc | 9 | ||||
| -rw-r--r-- | src/mem/cache/cache.cc | 6 | ||||
| -rw-r--r-- | src/mem/cache/noncoherent_cache.cc | 2 |
3 files changed, 9 insertions, 8 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 08cd09fc5..6049ca6a6 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -69,7 +69,8 @@ using namespace std; BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, BaseCache *_cache, const std::string &_label) - : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), + : QueuedSlavePort(_name, _cache, queue), + queue(*_cache, *this, true, _label), blocked(false), mustSendRetry(false), sendRetryEvent([this]{ processSendRetry(); }, _name) { @@ -228,7 +229,7 @@ BaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) // lat, neglecting responseLatency, modelling hit latency // just as the value of lat overriden by access(), which calls // the calculateAccessLatency() function. - cpuSidePort.schedTimingResp(pkt, request_time, true); + cpuSidePort.schedTimingResp(pkt, request_time); } else { DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, pkt->print()); @@ -400,7 +401,7 @@ BaseCache::handleUncacheableWriteResp(PacketPtr pkt) // Reset the bus additional time as it is now accounted for pkt->headerDelay = pkt->payloadDelay = 0; - cpuSidePort.schedTimingResp(pkt, completion_time, true); + cpuSidePort.schedTimingResp(pkt, completion_time); } void @@ -2400,7 +2401,7 @@ BaseCache::MemSidePort::MemSidePort(const std::string &_name, const std::string &_label) : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), _reqQueue(*_cache, *this, _snoopRespQueue, _label), - _snoopRespQueue(*_cache, *this, _label), cache(_cache) + _snoopRespQueue(*_cache, *this, true, _label), cache(_cache) { } diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index 90c4b9b5a..e23c4ef30 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -391,7 +391,7 @@ Cache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, // request_time is used here, taking into account lat and the delay // charged if the packet comes from the xbar. - cpuSidePort.schedTimingResp(pkt, request_time, true); + cpuSidePort.schedTimingResp(pkt, request_time); // If an outstanding request is in progress (we found an // MSHR) this is set to null @@ -802,7 +802,7 @@ Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk) } // Reset the bus additional time as it is now accounted for tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; - cpuSidePort.schedTimingResp(tgt_pkt, completion_time, true); + cpuSidePort.schedTimingResp(tgt_pkt, completion_time); break; case MSHR::Target::FromPrefetcher: @@ -932,7 +932,7 @@ Cache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, pkt->headerDelay = pkt->payloadDelay = 0; DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, pkt->print(), forward_time); - memSidePort.schedTimingSnoopResp(pkt, forward_time, true); + memSidePort.schedTimingSnoopResp(pkt, forward_time); } uint32_t diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc index ca282a38d..08cfdd654 100644 --- a/src/mem/cache/noncoherent_cache.cc +++ b/src/mem/cache/noncoherent_cache.cc @@ -288,7 +288,7 @@ NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, // Reset the bus additional time as it is now accounted for tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; - cpuSidePort.schedTimingResp(tgt_pkt, completion_time, true); + cpuSidePort.schedTimingResp(tgt_pkt, completion_time); break; case MSHR::Target::FromPrefetcher: |