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-rw-r--r--src/mem/cache/base.cc18
-rw-r--r--src/mem/cache/base.hh6
2 files changed, 7 insertions, 17 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 50622d776..19655a57e 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -185,23 +185,15 @@ BaseCache::init()
forwardSnoops = cpuSidePort.isSnooping();
}
-BaseMasterPort &
-BaseCache::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+BaseCache::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "mem_side") {
return memSidePort;
- } else {
- return MemObject::getMasterPort(if_name, idx);
- }
-}
-
-BaseSlavePort &
-BaseCache::getSlavePort(const std::string &if_name, PortID idx)
-{
- if (if_name == "cpu_side") {
+ } else if (if_name == "cpu_side") {
return cpuSidePort;
- } else {
- return MemObject::getSlavePort(if_name, idx);
+ } else {
+ return MemObject::getPort(if_name, idx);
}
}
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index a7b25ff2f..a45dcba6f 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -1028,10 +1028,8 @@ class BaseCache : public MemObject
void init() override;
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
- BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/**
* Query block size of a cache.