diff options
Diffstat (limited to 'src/mem/comm_monitor.cc')
| -rw-r--r-- | src/mem/comm_monitor.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc index fa1950be3..6077d2951 100644 --- a/src/mem/comm_monitor.cc +++ b/src/mem/comm_monitor.cc @@ -144,18 +144,17 @@ CommMonitor::recvTimingReq(PacketPtr pkt) const bool is_read = pkt->isRead(); const bool is_write = pkt->isWrite(); const bool expects_response( - pkt->needsResponse() && !pkt->memInhibitAsserted()); + pkt->needsResponse() && !pkt->cacheResponding()); // If a cache miss is served by a cache, a monitor near the memory // would see a request which needs a response, but this response - // would be inhibited and not come back from the memory. Therefore - // we additionally have to check the inhibit flag. + // would not come back from the memory. Therefore we additionally + // have to check the cacheResponding flag if (expects_response && !stats.disableLatencyHists) { pkt->pushSenderState(new CommMonitorSenderState(curTick())); } - // Attempt to send the packet (always succeeds for inhibited - // packets) + // Attempt to send the packet bool successful = masterPort.sendTimingReq(pkt); // If not successful, restore the sender state |