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-rw-r--r--src/mem/dramsim2.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index 5cde19cd8..6444f75d6 100644
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -148,7 +148,7 @@ class DRAMSim2 : public AbstractMemory
/**
* Event to schedule sending of responses
*/
- EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent;
+ EventFunctionWrapper sendResponseEvent;
/**
* Progress the controller one clock cycle.
@@ -158,7 +158,7 @@ class DRAMSim2 : public AbstractMemory
/**
* Event to schedule clock ticks
*/
- EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent;
+ EventFunctionWrapper tickEvent;
/**
* Upstream caches need this packet until true is returned, so