summaryrefslogtreecommitdiff
path: root/src/mem/noncoherent_bus.cc
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/noncoherent_bus.cc')
-rw-r--r--src/mem/noncoherent_bus.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/noncoherent_bus.cc b/src/mem/noncoherent_bus.cc
index f14f6e3d6..ae5344425 100644
--- a/src/mem/noncoherent_bus.cc
+++ b/src/mem/noncoherent_bus.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -55,8 +55,8 @@
#include "mem/noncoherent_bus.hh"
NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
- : BaseBus(p), reqLayer(*this, ".reqLayer", p->clock),
- respLayer(*this, ".respLayer", p->clock)
+ : BaseBus(p), reqLayer(*this, ".reqLayer"),
+ respLayer(*this, ".respLayer")
{
// create the ports based on the size of the master and slave
// vector ports, and the presence of the default port, the ports