diff options
Diffstat (limited to 'src/mem/port.hh')
| -rw-r--r-- | src/mem/port.hh | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/src/mem/port.hh b/src/mem/port.hh index 0d88441dc..39f6dead8 100644 --- a/src/mem/port.hh +++ b/src/mem/port.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012,2015 ARM Limited + * Copyright (c) 2011-2012,2015,2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -224,6 +224,19 @@ class MasterPort : public BaseMasterPort bool sendTimingReq(PacketPtr pkt); /** + * Check if the slave can handle a timing request. + * + * If the send cannot be handled at the moment, as indicated by + * the return value, then the sender will receive a recvReqRetry + * at which point it can re-issue a sendTimingReq. + * + * @param pkt Packet to send. + * + * @return If the send was succesful or not. + */ + bool tryTiming(PacketPtr pkt) const; + + /** * Attempt to send a timing snoop response packet to the slave * port by calling its corresponding receive function. If the send * does not succeed, as indicated by the return value, then the @@ -452,6 +465,13 @@ class SlavePort : public BaseSlavePort virtual bool recvTimingReq(PacketPtr pkt) = 0; /** + * Availability request from the master port. + */ + virtual bool tryTiming(PacketPtr pkt) { + panic("%s was not expecting a %s\n", name(), __func__); + } + + /** * Receive a timing snoop response from the master port. */ virtual bool recvTimingSnoopResp(PacketPtr pkt) |