diff options
Diffstat (limited to 'src/mem/probes')
-rw-r--r-- | src/mem/probes/SConscript | 3 | ||||
-rw-r--r-- | src/mem/probes/StackDistProbe.py | 64 | ||||
-rw-r--r-- | src/mem/probes/stack_dist.cc | 138 | ||||
-rw-r--r-- | src/mem/probes/stack_dist.hh | 91 |
4 files changed, 296 insertions, 0 deletions
diff --git a/src/mem/probes/SConscript b/src/mem/probes/SConscript index 3fe5752cc..7391545fb 100644 --- a/src/mem/probes/SConscript +++ b/src/mem/probes/SConscript @@ -41,3 +41,6 @@ Import('*') SimObject('BaseMemProbe.py') Source('base.cc') + +SimObject('StackDistProbe.py') +Source('stack_dist.cc') diff --git a/src/mem/probes/StackDistProbe.py b/src/mem/probes/StackDistProbe.py new file mode 100644 index 000000000..431e86463 --- /dev/null +++ b/src/mem/probes/StackDistProbe.py @@ -0,0 +1,64 @@ +# Copyright (c) 2014-2015 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Hansson +# Andreas Sandberg + +from m5.params import * +from m5.proxy import * +from BaseMemProbe import BaseMemProbe + +class StackDistProbe(BaseMemProbe): + type = 'StackDistProbe' + cxx_header = "mem/probes/stack_dist.hh" + + system = Param.System(Parent.any, + "System to use when determining system cache " + "line size") + + line_size = Param.Unsigned(Parent.cache_line_size, + "Cache line size in bytes (must be larger or " + "equal to the system's line size)") + + # enable verification stack + verify = Param.Bool(False, "Verify behaviuor with reference implementation") + + # linear histogram bins and enable/disable + linear_hist_bins = Param.Unsigned('16', "Bins in linear histograms") + disable_linear_hists = Param.Bool(False, "Disable linear histograms") + + # logarithmic histogram bins and enable/disable + log_hist_bins = Param.Unsigned('32', "Bins in logarithmic histograms") + disable_log_hists = Param.Bool(False, "Disable logarithmic histograms") diff --git a/src/mem/probes/stack_dist.cc b/src/mem/probes/stack_dist.cc new file mode 100644 index 000000000..c742cae7b --- /dev/null +++ b/src/mem/probes/stack_dist.cc @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2015 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Sandberg + */ + +#include "mem/probes/stack_dist.hh" + +#include "params/StackDistProbe.hh" +#include "sim/system.hh" + +StackDistProbe::StackDistProbe(StackDistProbeParams *p) + : BaseMemProbe(p), + lineSize(p->line_size), + disableLinearHists(p->disable_linear_hists), + disableLogHists(p->disable_log_hists), + calc(p->verify) +{ + fatal_if(p->system->cacheLineSize() > p->line_size, + "The stack distance probe must use a cache line size that is " + "larger or equal to the system's cahce line size."); +} + +void +StackDistProbe::regStats() +{ + const StackDistProbeParams *p( + dynamic_cast<const StackDistProbeParams *>(params())); + assert(p); + + using namespace Stats; + + readLinearHist + .init(p->linear_hist_bins) + .name(name() + ".readLinearHist") + .desc("Reads linear distribution") + .flags(disableLinearHists ? nozero : pdf); + + readLogHist + .init(p->log_hist_bins) + .name(name() + ".readLogHist") + .desc("Reads logarithmic distribution") + .flags(disableLogHists ? nozero : pdf); + + writeLinearHist + .init(p->linear_hist_bins) + .name(name() + ".writeLinearHist") + .desc("Writes linear distribution") + .flags(disableLinearHists ? nozero : pdf); + + writeLogHist + .init(p->log_hist_bins) + .name(name() + ".writeLogHist") + .desc("Writes logarithmic distribution") + .flags(disableLogHists ? nozero : pdf); + + infiniteSD + .name(name() + ".infinity") + .desc("Number of requests with infinite stack distance") + .flags(nozero); +} + +void +StackDistProbe::handleRequest(const PacketPtr &pkt) +{ + // only capturing read and write requests (which allocate in the + // cache) + if (!pkt->isRead() && !pkt->isWrite()) + return; + + // Align the address to a cache line size + const Addr aligned_addr(roundDown(pkt->getAddr(), lineSize)); + + // Calculate the stack distance + const uint64_t sd(calc.calcStackDistAndUpdate(aligned_addr).first); + if (sd == StackDistCalc::Infinity) { + infiniteSD++; + return; + } + + // Sample the stack distance of the address in linear bins + if (!disableLinearHists) { + if (pkt->isRead()) + readLinearHist.sample(sd); + else + writeLinearHist.sample(sd); + } + + if (!disableLogHists) { + int sd_lg2 = sd == 0 ? 1 : floorLog2(sd); + + // Sample the stack distance of the address in log bins + if (pkt->isRead()) + readLogHist.sample(sd_lg2); + else + writeLogHist.sample(sd_lg2); + } +} + + +StackDistProbe * +StackDistProbeParams::create() +{ + return new StackDistProbe(this); +} diff --git a/src/mem/probes/stack_dist.hh b/src/mem/probes/stack_dist.hh new file mode 100644 index 000000000..210800894 --- /dev/null +++ b/src/mem/probes/stack_dist.hh @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Sandberg + */ + +#ifndef __MEM_PROBES_STACK_DIST_HH__ +#define __MEM_PROBES_STACK_DIST_HH__ + +#include "mem/packet.hh" +#include "mem/probes/base.hh" +#include "mem/stack_dist_calc.hh" +#include "sim/stats.hh" + +struct StackDistProbeParams; + +class StackDistProbe : public BaseMemProbe +{ + public: + StackDistProbe(StackDistProbeParams *params); + + void regStats() M5_ATTR_OVERRIDE; + + protected: + void handleRequest(const PacketPtr &pkt) M5_ATTR_OVERRIDE; + + protected: + // Cache line size to simulate + const unsigned lineSize; + + // Disable the linear histograms + const bool disableLinearHists; + + // Disable the logarithmic histograms + const bool disableLogHists; + + protected: + // Reads linear histogram + Stats::Histogram readLinearHist; + + // Reads logarithmic histogram + Stats::SparseHistogram readLogHist; + + // Writes linear histogram + Stats::Histogram writeLinearHist; + + // Writes logarithmic histogram + Stats::SparseHistogram writeLogHist; + + // Writes logarithmic histogram + Stats::Scalar infiniteSD; + + protected: + StackDistCalc calc; +}; + + +#endif //__MEM_PROBES_STACK_DIST_HH__ |