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Diffstat (limited to 'src/mem/protocol/MESI_CMP_directory-L1cache.sm')
-rw-r--r--src/mem/protocol/MESI_CMP_directory-L1cache.sm80
1 files changed, 40 insertions, 40 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
index 5d7e2bcfb..48845fdc6 100644
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
@@ -125,7 +125,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
// TBE fields
structure(TBE, desc="...") {
- Address Address, desc="Physical address for this TBE";
+ Address Addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="data is dirty";
@@ -348,36 +348,36 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
// Response IntraChip L1 Network - response msg to this L1 cache
in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache, rank = 2) {
if (responseIntraChipL1Network_in.isReady()) {
- peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Address") {
+ peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Addr") {
assert(in_msg.Destination.isElement(machineID));
- Entry cache_entry := getCacheEntry(in_msg.Address);
- TBE tbe := L1_TBEs[in_msg.Address];
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L1_TBEs[in_msg.Addr];
if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
- trigger(Event:Data_Exclusive, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Data_Exclusive, in_msg.Addr, cache_entry, tbe);
} else if(in_msg.Type == CoherenceResponseType:DATA) {
- if ((getState(tbe, cache_entry, in_msg.Address) == State:IS ||
- getState(tbe, cache_entry, in_msg.Address) == State:IS_I ||
- getState(tbe, cache_entry, in_msg.Address) == State:PF_IS ||
- getState(tbe, cache_entry, in_msg.Address) == State:PF_IS_I) &&
+ if ((getState(tbe, cache_entry, in_msg.Addr) == State:IS ||
+ getState(tbe, cache_entry, in_msg.Addr) == State:IS_I ||
+ getState(tbe, cache_entry, in_msg.Addr) == State:PF_IS ||
+ getState(tbe, cache_entry, in_msg.Addr) == State:PF_IS_I) &&
machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
- trigger(Event:DataS_fromL1, in_msg.Address, cache_entry, tbe);
+ trigger(Event:DataS_fromL1, in_msg.Addr, cache_entry, tbe);
} else if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
- trigger(Event:Data_all_Acks, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Data_all_Acks, in_msg.Addr, cache_entry, tbe);
} else {
- trigger(Event:Data, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
}
} else if (in_msg.Type == CoherenceResponseType:ACK) {
if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
- trigger(Event:Ack_all, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
} else {
- trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
}
} else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
- trigger(Event:WB_Ack, in_msg.Address, cache_entry, tbe);
+ trigger(Event:WB_Ack, in_msg.Addr, cache_entry, tbe);
} else {
error("Invalid L1 response type");
}
@@ -388,22 +388,22 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
// Request InterChip network - request from this L1 cache to the shared L2
in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache, rank = 1) {
if(requestIntraChipL1Network_in.isReady()) {
- peek(requestIntraChipL1Network_in, RequestMsg, block_on="Address") {
+ peek(requestIntraChipL1Network_in, RequestMsg, block_on="Addr") {
assert(in_msg.Destination.isElement(machineID));
- Entry cache_entry := getCacheEntry(in_msg.Address);
- TBE tbe := L1_TBEs[in_msg.Address];
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L1_TBEs[in_msg.Addr];
if (in_msg.Type == CoherenceRequestType:INV) {
- trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
} else if (in_msg.Type == CoherenceRequestType:GETX ||
in_msg.Type == CoherenceRequestType:UPGRADE) {
// upgrade transforms to GETX due to race
- trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
} else if (in_msg.Type == CoherenceRequestType:GETS) {
- trigger(Event:Fwd_GETS, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Fwd_GETS, in_msg.Addr, cache_entry, tbe);
} else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
- trigger(Event:Fwd_GET_INSTR, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Fwd_GET_INSTR, in_msg.Addr, cache_entry, tbe);
} else {
error("Invalid forwarded request type");
}
@@ -495,7 +495,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(a_issueGETS, "a", desc="Issue GETS") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -513,7 +513,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
peek(optionalQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg,
latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -530,7 +530,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GET_INSTR;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -549,7 +549,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
peek(optionalQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg,
latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GET_INSTR;
out_msg.Requestor := machineID;
out_msg.Destination.add(
@@ -568,7 +568,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(b_issueGETX, "b", desc="Issue GETX") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
DPRINTF(RubySlicc, "%s\n", machineID);
@@ -587,7 +587,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
peek(optionalQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg,
latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
DPRINTF(RubySlicc, "%s\n", machineID);
@@ -609,7 +609,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(c_issueUPGRADE, "c", desc="Issue GETX") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:UPGRADE;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -627,7 +627,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
peek(requestIntraChipL1Network_in, RequestMsg) {
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -641,7 +641,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") {
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -656,7 +656,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
peek(requestIntraChipL1Network_in, RequestMsg) {
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
assert(is_valid(tbe));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := tbe.DataBlk;
out_msg.Dirty := tbe.Dirty;
@@ -670,7 +670,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
assert(is_valid(tbe));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := tbe.DataBlk;
out_msg.Dirty := tbe.Dirty;
@@ -684,7 +684,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") {
peek(requestIntraChipL1Network_in, RequestMsg) {
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
@@ -696,7 +696,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -710,7 +710,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
assert(is_valid(tbe));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := tbe.DataBlk;
out_msg.Dirty := tbe.Dirty;
@@ -724,7 +724,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
peek(requestIntraChipL1Network_in, RequestMsg) {
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
@@ -744,7 +744,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(g_issuePUTX, "g", desc="send data to the L2 cache") {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:PUTX;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -761,7 +761,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:UNBLOCK;
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -773,7 +773,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 01:13:46 +0000