diff options
Diffstat (limited to 'src/mem/protocol/MESI_CMP_directory-L2cache.sm')
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L2cache.sm | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm index 6044f5233..a8fcb07d1 100644 --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm @@ -56,7 +56,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") NP, AccessPermission:Invalid, desc="Not present in either cache"; SS, AccessPermission:Read_Only, desc="L2 cache entry Shared, also present in one or more L1s"; M, AccessPermission:Read_Write, desc="L2 cache entry Modified, not present in any L1s", format="!b"; - MT, AccessPermission:Invalid, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b"; + MT, AccessPermission:Maybe_Stale, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b"; // L2 replacement M_I, AccessPermission:Busy, desc="L2 cache replacing, have all acks, sent dirty data to memory, waiting for ACK from memory"; @@ -217,17 +217,24 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") AccessPermission getAccessPermission(Address addr) { TBE tbe := L2_TBEs[addr]; if(is_valid(tbe)) { + DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState)); return L2Cache_State_to_permission(tbe.TBEState); } Entry cache_entry := getCacheEntry(addr); if(is_valid(cache_entry)) { + DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(cache_entry.CacheState)); return L2Cache_State_to_permission(cache_entry.CacheState); } + DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent); return AccessPermission:NotPresent; } + DataBlock getDataBlock(Address addr), return_by_ref="yes" { + return getCacheEntry(addr).DataBlk; + } + void setAccessPermission(Entry cache_entry, Address addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L2Cache_State_to_permission(state)); |