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Diffstat (limited to 'src/mem/protocol/MESI_CMP_directory-mem.sm')
-rw-r--r--src/mem/protocol/MESI_CMP_directory-mem.sm79
1 files changed, 31 insertions, 48 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-mem.sm b/src/mem/protocol/MESI_CMP_directory-mem.sm
index f5a2e431b..82902e8af 100644
--- a/src/mem/protocol/MESI_CMP_directory-mem.sm
+++ b/src/mem/protocol/MESI_CMP_directory-mem.sm
@@ -40,13 +40,11 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
int directory_latency
{
- MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false";
- MessageBuffer responseToDir, network="From", virtual_network="3", ordered="false";
- MessageBuffer responseFromDir, network="To", virtual_network="3", ordered="false";
-
- MessageBuffer dmaRequestFromDir, network="To", virtual_network="6", ordered="true";
- MessageBuffer dmaRequestToDir, network="From", virtual_network="7", ordered="true";
+ MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false";
+ MessageBuffer responseToDir, network="From", virtual_network="1", ordered="false";
+ MessageBuffer requestFromDir, network="To", virtual_network="0", ordered="false";
+ MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false";
// STATES
enumeration(State, desc="Directory states", default="Directory_State_I") {
@@ -167,32 +165,19 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
// ** OUT_PORTS **
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
out_port(memQueue_out, MemoryMsg, memBuffer);
- out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaRequestFromDir);
// ** IN_PORTS **
-//added by SS for dma
- in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
- if (dmaRequestQueue_in.isReady()) {
- peek(dmaRequestQueue_in, DMARequestMsg) {
- if (in_msg.Type == DMARequestType:READ) {
- trigger(Event:DMA_READ, in_msg.LineAddress);
- } else if (in_msg.Type == DMARequestType:WRITE) {
- trigger(Event:DMA_WRITE, in_msg.LineAddress);
- } else {
- error("Invalid message");
- }
- }
- }
- }
-
-
in_port(requestNetwork_in, RequestMsg, requestToDir) {
if (requestNetwork_in.isReady()) {
peek(requestNetwork_in, RequestMsg) {
assert(in_msg.Destination.isElement(machineID));
if (isGETRequest(in_msg.Type)) {
trigger(Event:Fetch, in_msg.Address);
+ } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
+ trigger(Event:DMA_READ, makeLineAddress(in_msg.Address));
+ } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
+ trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address));
} else {
DEBUG_EXPR(in_msg);
error("Invalid message");
@@ -328,7 +313,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
}
//added by SS for dma
action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
- peek(dmaRequestQueue_in, DMARequestMsg) {
+ peek(requestNetwork_in, RequestMsg) {
enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
out_msg.Address := address;
out_msg.Type := MemoryRequestType:MEMORY_READ;
@@ -342,14 +327,14 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
}
action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
- dmaRequestQueue_in.dequeue();
+ requestNetwork_in.dequeue();
}
action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
peek(memQueue_in, MemoryMsg) {
- enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) {
- out_msg.PhysicalAddress := address;
- out_msg.Type := DMAResponseType:DATA;
+ enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Address := address;
+ out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
out_msg.Destination.add(map_Address_to_DMA(address));
out_msg.MessageSize := MessageSizeType:Response_Data;
@@ -358,15 +343,13 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
}
action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
- peek(dmaRequestQueue_in, DMARequestMsg) {
- //directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, in_msg.Offset, in_msg.Len);
-
- directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.PhysicalAddress), in_msg.Len);
+ peek(requestNetwork_in, RequestMsg) {
+ directory[address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
}
}
action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
- peek(dmaRequestQueue_in, DMARequestMsg) {
+ peek(requestNetwork_in, RequestMsg) {
enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
out_msg.Address := address;
out_msg.Type := MemoryRequestType:MEMORY_WB;
@@ -384,9 +367,9 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
}
action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
- enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) {
- out_msg.PhysicalAddress := address;
- out_msg.Type := DMAResponseType:ACK;
+ enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Address := address;
+ out_msg.Type := CoherenceResponseType:ACK;
out_msg.Destination.add(map_Address_to_DMA(address));
out_msg.MessageSize := MessageSizeType:Writeback_Control;
}
@@ -397,7 +380,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
}
action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") {
- dmaRequestQueue_in.recycle();
+ requestNetwork_in.recycle();
}
@@ -410,12 +393,12 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
- peek(dmaRequestQueue_in, DMARequestMsg) {
+ peek(requestNetwork_in, RequestMsg) {
enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceResponseType:INV;
out_msg.Sender := machineID;
- out_msg.Destination := directory[in_msg.PhysicalAddress].Owner;
+ out_msg.Destination := directory[address].Owner;
out_msg.MessageSize := MessageSizeType:Response_Control;
}
}
@@ -424,9 +407,9 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
peek(responseNetwork_in, ResponseMsg) {
- enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) {
- out_msg.PhysicalAddress := address;
- out_msg.Type := DMAResponseType:DATA;
+ enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Address := address;
+ out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
out_msg.Destination.add(map_Address_to_DMA(address));
out_msg.MessageSize := MessageSizeType:Response_Data;
@@ -439,10 +422,10 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
}
action(v_allocateTBE, "v", desc="Allocate TBE") {
- peek(dmaRequestQueue_in, DMARequestMsg) {
+ peek(requestNetwork_in, RequestMsg) {
TBEs.allocate(address);
TBEs[address].DataBlk := in_msg.DataBlk;
- TBEs[address].PhysicalAddress := in_msg.PhysicalAddress;
+ TBEs[address].PhysicalAddress := in_msg.Address;
TBEs[address].Len := in_msg.Len;
}
}
@@ -514,7 +497,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
//added by SS for dma support
transition(I, DMA_READ, ID) {
qf_queueMemoryFetchRequestDMA;
- p_popIncomingDMARequestQueue;
+ j_popIncomingRequestQueue;
}
transition(ID, Memory_Data, I) {
@@ -525,7 +508,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
transition(I, DMA_WRITE, ID_W) {
dw_writeDMAData;
qw_queueMemoryWBRequest_partial;
- p_popIncomingDMARequestQueue;
+ j_popIncomingRequestQueue;
}
transition(ID_W, Memory_Ack, I) {
@@ -544,7 +527,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
transition(M, DMA_READ, M_DRD) {
inv_sendCacheInvalidate;
- p_popIncomingDMARequestQueue;
+ j_popIncomingRequestQueue;
}
transition(M_DRD, Data, M_DRDI) {
@@ -563,7 +546,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
transition(M, DMA_WRITE, M_DWR) {
v_allocateTBE;
inv_sendCacheInvalidate;
- p_popIncomingDMARequestQueue;
+ j_popIncomingRequestQueue;
}
transition(M_DWR, Data, M_DWRI) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 11:07:45 +0000