diff options
Diffstat (limited to 'src/mem/protocol/MESI_Three_Level-L0cache.sm')
| -rw-r--r-- | src/mem/protocol/MESI_Three_Level-L0cache.sm | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm index 47a41b83a..5e49d5b13 100644 --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm @@ -36,10 +36,10 @@ machine(L0Cache, "MESI Directory L0 Cache") { // NODE L0 CACHE // From this node's L0 cache to the network - MessageBuffer bufferFromCache, network="To", physical_network="0", ordered="true"; + MessageBuffer bufferToL1, network="To", physical_network="0", ordered="true"; // To this node's L0 cache FROM the network - MessageBuffer bufferToCache, network="From", physical_network="0", ordered="true"; + MessageBuffer bufferFromL1, network="From", physical_network="0", ordered="true"; // Message queue between this controller and the processor MessageBuffer mandatoryQueue, ordered="false"; @@ -237,10 +237,10 @@ machine(L0Cache, "MESI Directory L0 Cache") return tbe.pendingAcks; } - out_port(requestNetwork_out, CoherenceMsg, bufferFromCache); + out_port(requestNetwork_out, CoherenceMsg, bufferToL1); // Messages for this L0 cache from the L1 cache - in_port(messgeBuffer_in, CoherenceMsg, bufferToCache, rank = 1) { + in_port(messgeBuffer_in, CoherenceMsg, bufferFromL1, rank = 1) { if (messgeBuffer_in.isReady()) { peek(messgeBuffer_in, CoherenceMsg, block_on="Addr") { assert(in_msg.Destination == machineID); |