diff options
Diffstat (limited to 'src/mem/protocol/MESI_Three_Level-L1cache.sm')
-rw-r--r-- | src/mem/protocol/MESI_Three_Level-L1cache.sm | 94 |
1 files changed, 47 insertions, 47 deletions
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm index 6b169508a..e999eee05 100644 --- a/src/mem/protocol/MESI_Three_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm @@ -133,7 +133,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") // TBE fields structure(TBE, desc="...") { - Address Addr, desc="Physical address for this TBE"; + Address addr, desc="Physical address for this TBE"; State TBEState, desc="Transient state"; DataBlock DataBlk, desc="Buffer for the data block"; bool Dirty, default="false", desc="data is dirty"; @@ -270,30 +270,30 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") peek(responseNetwork_in, ResponseMsg) { assert(in_msg.Destination.isElement(machineID)); - Entry cache_entry := getCacheEntry(in_msg.Addr); - TBE tbe := TBEs[in_msg.Addr]; + Entry cache_entry := getCacheEntry(in_msg.addr); + TBE tbe := TBEs[in_msg.addr]; if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) { - trigger(Event:Data_Exclusive, in_msg.Addr, cache_entry, tbe); + trigger(Event:Data_Exclusive, in_msg.addr, cache_entry, tbe); } else if(in_msg.Type == CoherenceResponseType:DATA) { - if (getState(tbe, cache_entry, in_msg.Addr) == State:IS && + if (getState(tbe, cache_entry, in_msg.addr) == State:IS && machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) { - trigger(Event:DataS_fromL1, in_msg.Addr, cache_entry, tbe); + trigger(Event:DataS_fromL1, in_msg.addr, cache_entry, tbe); } else if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) { - trigger(Event:Data_all_Acks, in_msg.Addr, cache_entry, tbe); + trigger(Event:Data_all_Acks, in_msg.addr, cache_entry, tbe); } else { - trigger(Event:Data, in_msg.Addr, cache_entry, tbe); + trigger(Event:Data, in_msg.addr, cache_entry, tbe); } } else if (in_msg.Type == CoherenceResponseType:ACK) { if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) { - trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe); + trigger(Event:Ack_all, in_msg.addr, cache_entry, tbe); } else { - trigger(Event:Ack, in_msg.Addr, cache_entry, tbe); + trigger(Event:Ack, in_msg.addr, cache_entry, tbe); } } else if (in_msg.Type == CoherenceResponseType:WB_ACK) { - trigger(Event:WB_Ack, in_msg.Addr, cache_entry, tbe); + trigger(Event:WB_Ack, in_msg.addr, cache_entry, tbe); } else { error("Invalid L1 response type"); } @@ -306,30 +306,30 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") if(requestNetwork_in.isReady()) { peek(requestNetwork_in, RequestMsg) { assert(in_msg.Destination.isElement(machineID)); - Entry cache_entry := getCacheEntry(in_msg.Addr); - TBE tbe := TBEs[in_msg.Addr]; + Entry cache_entry := getCacheEntry(in_msg.addr); + TBE tbe := TBEs[in_msg.addr]; if (in_msg.Type == CoherenceRequestType:INV) { if (is_valid(cache_entry) && inL0Cache(cache_entry.CacheState)) { - trigger(Event:L0_Invalidate_Else, in_msg.Addr, + trigger(Event:L0_Invalidate_Else, in_msg.addr, cache_entry, tbe); } else { - trigger(Event:Inv, in_msg.Addr, cache_entry, tbe); + trigger(Event:Inv, in_msg.addr, cache_entry, tbe); } } else if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:UPGRADE) { if (is_valid(cache_entry) && inL0Cache(cache_entry.CacheState)) { - trigger(Event:L0_Invalidate_Else, in_msg.Addr, + trigger(Event:L0_Invalidate_Else, in_msg.addr, cache_entry, tbe); } else { - trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe); + trigger(Event:Fwd_GETX, in_msg.addr, cache_entry, tbe); } } else if (in_msg.Type == CoherenceRequestType:GETS) { if (is_valid(cache_entry) && inL0Cache(cache_entry.CacheState)) { - trigger(Event:L0_Invalidate_Else, in_msg.Addr, + trigger(Event:L0_Invalidate_Else, in_msg.addr, cache_entry, tbe); } else { - trigger(Event:Fwd_GETS, in_msg.Addr, cache_entry, tbe); + trigger(Event:Fwd_GETS, in_msg.addr, cache_entry, tbe); } } else { error("Invalid forwarded request type"); @@ -342,36 +342,36 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") in_port(messageBufferFromL0_in, CoherenceMsg, bufferFromL0, rank = 0) { if (messageBufferFromL0_in.isReady()) { peek(messageBufferFromL0_in, CoherenceMsg) { - Entry cache_entry := getCacheEntry(in_msg.Addr); - TBE tbe := TBEs[in_msg.Addr]; + Entry cache_entry := getCacheEntry(in_msg.addr); + TBE tbe := TBEs[in_msg.addr]; if(in_msg.Class == CoherenceClass:INV_DATA) { - trigger(Event:L0_DataAck, in_msg.Addr, cache_entry, tbe); + trigger(Event:L0_DataAck, in_msg.addr, cache_entry, tbe); } else if (in_msg.Class == CoherenceClass:INV_ACK) { - trigger(Event:L0_Ack, in_msg.Addr, cache_entry, tbe); + trigger(Event:L0_Ack, in_msg.addr, cache_entry, tbe); } else { if (is_valid(cache_entry)) { trigger(mandatory_request_type_to_event(in_msg.Class), - in_msg.Addr, cache_entry, tbe); + in_msg.addr, cache_entry, tbe); } else { - if (cache.cacheAvail(in_msg.Addr)) { + if (cache.cacheAvail(in_msg.addr)) { // L1 does't have the line, but we have space for it // in the L1 let's see if the L2 has it trigger(mandatory_request_type_to_event(in_msg.Class), - in_msg.Addr, cache_entry, tbe); + in_msg.addr, cache_entry, tbe); } else { // No room in the L1, so we need to make room in the L1 Entry victim_entry := - getCacheEntry(cache.cacheProbe(in_msg.Addr)); - TBE victim_tbe := TBEs[cache.cacheProbe(in_msg.Addr)]; + getCacheEntry(cache.cacheProbe(in_msg.addr)); + TBE victim_tbe := TBEs[cache.cacheProbe(in_msg.addr)]; if (is_valid(victim_entry) && inL0Cache(victim_entry.CacheState)) { trigger(Event:L0_Invalidate_Own, - cache.cacheProbe(in_msg.Addr), + cache.cacheProbe(in_msg.addr), victim_entry, victim_tbe); } else { trigger(Event:L1_Replacement, - cache.cacheProbe(in_msg.Addr), + cache.cacheProbe(in_msg.addr), victim_entry, victim_tbe); } } @@ -385,7 +385,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(a_issueGETS, "a", desc="Issue GETS") { peek(messageBufferFromL0_in, CoherenceMsg) { enqueue(requestNetwork_out, RequestMsg, l1_request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, @@ -401,7 +401,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(b_issueGETX, "b", desc="Issue GETX") { peek(messageBufferFromL0_in, CoherenceMsg) { enqueue(requestNetwork_out, RequestMsg, l1_request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; DPRINTF(RubySlicc, "%s\n", machineID); @@ -418,7 +418,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(c_issueUPGRADE, "c", desc="Issue GETX") { peek(messageBufferFromL0_in, CoherenceMsg) { enqueue(requestNetwork_out, RequestMsg, l1_request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:UPGRADE; out_msg.Requestor := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, @@ -435,7 +435,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") peek(requestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := cache_entry.DataBlk; out_msg.Dirty := cache_entry.Dirty; @@ -449,7 +449,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") { enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := cache_entry.DataBlk; out_msg.Dirty := cache_entry.Dirty; @@ -464,7 +464,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") peek(requestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(tbe)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := tbe.DataBlk; out_msg.Dirty := tbe.Dirty; @@ -478,7 +478,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") { enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(tbe)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := tbe.DataBlk; out_msg.Dirty := tbe.Dirty; @@ -492,7 +492,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") { peek(requestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -504,7 +504,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(f_sendDataToL2, "f", desc="send data to the L2 cache") { enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := cache_entry.DataBlk; out_msg.Dirty := cache_entry.Dirty; @@ -518,7 +518,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") { enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(tbe)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := tbe.DataBlk; out_msg.Dirty := tbe.Dirty; @@ -532,7 +532,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(fi_sendInvAck, "fi", desc="send data to the L2 cache") { peek(requestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -544,7 +544,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(forward_eviction_to_L0, "\cc", desc="sends eviction information to the processor") { enqueue(bufferToL0_out, CoherenceMsg, l1_request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Class := CoherenceClass:INV; out_msg.Sender := machineID; out_msg.Dest := createMachineID(MachineType:L0Cache, version); @@ -555,7 +555,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(g_issuePUTX, "g", desc="send data to the L2 cache") { enqueue(requestNetwork_out, RequestMsg, l1_response_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:PUTX; out_msg.Dirty := cache_entry.Dirty; out_msg.Requestor:= machineID; @@ -572,7 +572,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(j_sendUnblock, "j", desc="send unblock to the L2 cache") { enqueue(unblockNetwork_out, ResponseMsg, to_l2_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, @@ -584,7 +584,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") { enqueue(unblockNetwork_out, ResponseMsg, to_l2_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK; out_msg.Sender := machineID; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, @@ -599,7 +599,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") enqueue(bufferToL0_out, CoherenceMsg, l1_response_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Class := CoherenceClass:DATA; out_msg.Sender := machineID; out_msg.Dest := createMachineID(MachineType:L0Cache, version); @@ -612,7 +612,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") enqueue(bufferToL0_out, CoherenceMsg, l1_response_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Class := CoherenceClass:DATA_EXCLUSIVE; out_msg.Sender := machineID; out_msg.Dest := createMachineID(MachineType:L0Cache, version); |