diff options
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-L1cache.sm')
| -rw-r--r-- | src/mem/protocol/MESI_Two_Level-L1cache.sm | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index 184f735c7..8033e5983 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -61,10 +61,13 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") // a L2 bank -> this L1 MessageBuffer * responseToL1Cache, network="From", virtual_network="1", vnet_type="response"; -{ + // Request Buffer for prefetches - MessageBuffer optionalQueue; + MessageBuffer * optionalQueue; + // Buffer for requests generated by the processor core. + MessageBuffer * mandatoryQueue; +{ // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states @@ -151,8 +154,6 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; - MessageBuffer mandatoryQueue; - int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; void set_cache_entry(AbstractCacheEntry a); |