diff options
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-L1cache.sm')
-rw-r--r-- | src/mem/protocol/MESI_Two_Level-L1cache.sm | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index f5feb7e23..8496fda61 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -981,6 +981,12 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP") sequencer.readCallback(address, cache_entry.DataBlk); } + action(h_spec_load_miss, "hsm", + desc="Notify sequencer the spec load misses.") + { + sequencer.readCallback(address, cache_entry.DataBlk, true); + } + action(h_ifetch_hit, "hi", desc="Notify sequencer the instruction fetch completed.") { assert(is_valid(cache_entry)); @@ -1222,8 +1228,7 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP") } transition({NP,I}, SpecLoad, IX) { - iw_allocateTBEWithoutCacheEntry; - as_issueGETSPEC; + h_spec_load_miss; k_popMandatoryQueue; } |