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Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-L2cache.sm')
-rw-r--r--src/mem/protocol/MESI_Two_Level-L2cache.sm32
1 files changed, 16 insertions, 16 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm
index 5c240035a..7cd5560fc 100644
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm
@@ -378,7 +378,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
peek(L1RequestL2Network_in, RequestMsg) {
- enqueue(DirRequestL2Network_out, RequestMsg, latency=l2_request_latency) {
+ enqueue(DirRequestL2Network_out, RequestMsg, l2_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
@@ -390,7 +390,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
peek(L1RequestL2Network_in, RequestMsg) {
- enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) {
+ enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := in_msg.Type;
@@ -402,7 +402,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
}
action(c_exclusiveReplacement, "c", desc="Send data to memory") {
- enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:MEMORY_DATA;
@@ -415,7 +415,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
}
action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
- enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
@@ -425,7 +425,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
}
action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
- enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
assert(is_valid(tbe));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:MEMORY_DATA;
@@ -439,7 +439,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") {
peek(L1RequestL2Network_in, RequestMsg) {
- enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -458,7 +458,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") {
peek(L1RequestL2Network_in, RequestMsg) {
- enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
@@ -477,7 +477,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
peek(L1RequestL2Network_in, RequestMsg) {
- enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -493,7 +493,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") {
assert(is_valid(tbe));
assert(tbe.L1_GetS_IDs.count() > 0);
- enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -507,7 +507,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") {
assert(is_valid(tbe));
assert(tbe.L1_GetS_IDs.count() == 1);
- enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
@@ -519,7 +519,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
}
action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") {
- enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
assert(is_valid(tbe));
assert(is_valid(cache_entry));
out_msg.Addr := address;
@@ -535,7 +535,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
}
action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
- enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) {
+ enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:INV;
@@ -547,7 +547,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") {
peek(L1RequestL2Network_in, RequestMsg) {
- enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) {
+ enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:INV;
@@ -560,7 +560,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") {
peek(L1RequestL2Network_in, RequestMsg) {
- enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) {
+ enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:INV;
@@ -670,7 +670,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(t_sendWBAck, "t", desc="Send writeback ACK") {
peek(L1RequestL2Network_in, RequestMsg) {
- enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:WB_ACK;
out_msg.Sender := machineID;
@@ -682,7 +682,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") {
peek(L1RequestL2Network_in, RequestMsg) {
- enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) {
+ enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:ACK;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 05:14:47 +0000