diff options
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-L2cache.sm')
-rw-r--r-- | src/mem/protocol/MESI_Two_Level-L2cache.sm | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm index f4809959d..ede420626 100644 --- a/src/mem/protocol/MESI_Two_Level-L2cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm @@ -212,13 +212,28 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") return AccessPermission:NotPresent; } - DataBlock getDataBlock(Address addr), return_by_ref="yes" { + void functionalRead(Address addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - return tbe.DataBlk; + testAndRead(addr, tbe.DataBlk, pkt); + } else { + testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); + } + } + + int functionalWrite(Address addr, Packet *pkt) { + int num_functional_writes := 0; + + TBE tbe := TBEs[addr]; + if(is_valid(tbe)) { + num_functional_writes := num_functional_writes + + testAndWrite(addr, tbe.DataBlk, pkt); + return num_functional_writes; } - return getCacheEntry(addr).DataBlk; + num_functional_writes := num_functional_writes + + testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); + return num_functional_writes; } void setAccessPermission(Entry cache_entry, Address addr, State state) { |