diff options
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-L2cache.sm')
-rw-r--r-- | src/mem/protocol/MESI_Two_Level-L2cache.sm | 90 |
1 files changed, 45 insertions, 45 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm index 1d1dbaa09..59aff8807 100644 --- a/src/mem/protocol/MESI_Two_Level-L2cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm @@ -129,7 +129,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") // TBE fields structure(TBE, desc="...") { - Address Addr, desc="Physical address for this TBE"; + Address addr, desc="Physical address for this TBE"; State TBEState, desc="Transient state"; DataBlock DataBlk, desc="Buffer for the data block"; bool Dirty, default="false", desc="Data is Dirty"; @@ -287,17 +287,17 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) { if(L1unblockNetwork_in.isReady()) { peek(L1unblockNetwork_in, ResponseMsg) { - Entry cache_entry := getCacheEntry(in_msg.Addr); - TBE tbe := TBEs[in_msg.Addr]; + Entry cache_entry := getCacheEntry(in_msg.addr); + TBE tbe := TBEs[in_msg.addr]; DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n", - in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr), + in_msg.addr, getState(tbe, cache_entry, in_msg.addr), in_msg.Sender, in_msg.Type, in_msg.Destination); assert(in_msg.Destination.isElement(machineID)); if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) { - trigger(Event:Exclusive_Unblock, in_msg.Addr, cache_entry, tbe); + trigger(Event:Exclusive_Unblock, in_msg.addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) { - trigger(Event:Unblock, in_msg.Addr, cache_entry, tbe); + trigger(Event:Unblock, in_msg.addr, cache_entry, tbe); } else { error("unknown unblock message"); } @@ -311,21 +311,21 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") peek(responseL2Network_in, ResponseMsg) { // test wether it's from a local L1 or an off chip source assert(in_msg.Destination.isElement(machineID)); - Entry cache_entry := getCacheEntry(in_msg.Addr); - TBE tbe := TBEs[in_msg.Addr]; + Entry cache_entry := getCacheEntry(in_msg.addr); + TBE tbe := TBEs[in_msg.addr]; if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) { if(in_msg.Type == CoherenceResponseType:DATA) { if (in_msg.Dirty) { - trigger(Event:WB_Data, in_msg.Addr, cache_entry, tbe); + trigger(Event:WB_Data, in_msg.addr, cache_entry, tbe); } else { - trigger(Event:WB_Data_clean, in_msg.Addr, cache_entry, tbe); + trigger(Event:WB_Data_clean, in_msg.addr, cache_entry, tbe); } } else if (in_msg.Type == CoherenceResponseType:ACK) { if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) { - trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe); + trigger(Event:Ack_all, in_msg.addr, cache_entry, tbe); } else { - trigger(Event:Ack, in_msg.Addr, cache_entry, tbe); + trigger(Event:Ack, in_msg.addr, cache_entry, tbe); } } else { error("unknown message type"); @@ -333,11 +333,11 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } else { // external message if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) { - trigger(Event:Mem_Data, in_msg.Addr, cache_entry, tbe); + trigger(Event:Mem_Data, in_msg.addr, cache_entry, tbe); } else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) { - trigger(Event:Mem_Ack, in_msg.Addr, cache_entry, tbe); + trigger(Event:Mem_Ack, in_msg.addr, cache_entry, tbe); } else if(in_msg.Type == CoherenceResponseType:INV) { - trigger(Event:MEM_Inv, in_msg.Addr, cache_entry, tbe); + trigger(Event:MEM_Inv, in_msg.addr, cache_entry, tbe); } else { error("unknown message type"); } @@ -350,11 +350,11 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) { if(L1RequestL2Network_in.isReady()) { peek(L1RequestL2Network_in, RequestMsg) { - Entry cache_entry := getCacheEntry(in_msg.Addr); - TBE tbe := TBEs[in_msg.Addr]; + Entry cache_entry := getCacheEntry(in_msg.addr); + TBE tbe := TBEs[in_msg.addr]; DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n", - in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr), + in_msg.addr, getState(tbe, cache_entry, in_msg.addr), in_msg.Requestor, in_msg.Type, in_msg.Destination); assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache); @@ -362,24 +362,24 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") if (is_valid(cache_entry)) { // The L2 contains the block, so proceeded with handling the request - trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr, + trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.addr, in_msg.Requestor, cache_entry), - in_msg.Addr, cache_entry, tbe); + in_msg.addr, cache_entry, tbe); } else { - if (L2cache.cacheAvail(in_msg.Addr)) { + if (L2cache.cacheAvail(in_msg.addr)) { // L2 does't have the line, but we have space for it in the L2 - trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr, + trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.addr, in_msg.Requestor, cache_entry), - in_msg.Addr, cache_entry, tbe); + in_msg.addr, cache_entry, tbe); } else { // No room in the L2, so we need to make room before handling the request - Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.Addr)); + Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.addr)); if (isDirty(L2cache_entry)) { - trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Addr), - L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.Addr)]); + trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.addr), + L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.addr)]); } else { - trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.Addr), - L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.Addr)]); + trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.addr), + L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.addr)]); } } } @@ -393,7 +393,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(a_issueFetchToMemory, "a", desc="fetch data from memory") { peek(L1RequestL2Network_in, RequestMsg) { enqueue(DirRequestL2Network_out, RequestMsg, l2_request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -406,7 +406,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") peek(L1RequestL2Network_in, RequestMsg) { enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; out_msg.Destination.add(cache_entry.Exclusive); @@ -418,7 +418,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(c_exclusiveReplacement, "c", desc="Send data to memory") { enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:MEMORY_DATA; out_msg.Sender := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -430,7 +430,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") { enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -441,7 +441,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") { enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { assert(is_valid(tbe)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:MEMORY_DATA; out_msg.Sender := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -455,7 +455,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") peek(L1RequestL2Network_in, RequestMsg) { enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -474,7 +474,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") peek(L1RequestL2Network_in, RequestMsg) { enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -493,7 +493,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") peek(L1RequestL2Network_in, RequestMsg) { enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -509,7 +509,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") assert(tbe.L1_GetS_IDs.count() > 0); enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes @@ -523,7 +523,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") assert(tbe.L1_GetS_IDs.count() == 1); enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes @@ -536,14 +536,14 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) { assert(is_valid(tbe)); assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.Destination.add(tbe.L1_GetX_ID); DPRINTF(RubySlicc, "%s\n", out_msg.Destination); out_msg.DataBlk := cache_entry.DataBlk; DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n", - out_msg.Addr, out_msg.Destination, out_msg.DataBlk); + out_msg.addr, out_msg.Destination, out_msg.DataBlk); out_msg.MessageSize := MessageSizeType:Response_Data; } } @@ -551,7 +551,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") { enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := machineID; out_msg.Destination := cache_entry.Sharers; @@ -563,7 +563,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") peek(L1RequestL2Network_in, RequestMsg) { enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := in_msg.Requestor; out_msg.Destination := cache_entry.Sharers; @@ -576,7 +576,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") peek(L1RequestL2Network_in, RequestMsg) { enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := in_msg.Requestor; out_msg.Destination := cache_entry.Sharers; @@ -685,7 +685,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(t_sendWBAck, "t", desc="Send writeback ACK") { peek(L1RequestL2Network_in, RequestMsg) { enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:WB_ACK; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -698,7 +698,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") peek(L1RequestL2Network_in, RequestMsg) { enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); |