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Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-dma.sm')
-rw-r--r--src/mem/protocol/MESI_Two_Level-dma.sm6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm
index 3d9f2336f..a1967c2d9 100644
--- a/src/mem/protocol/MESI_Two_Level-dma.sm
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm
@@ -32,9 +32,9 @@ machine(DMA, "DMA Controller")
Cycles request_latency := 6;
MessageBuffer * responseFromDir, network="From", virtual_network="1",
- ordered="true", vnet_type="response";
+ vnet_type="response";
MessageBuffer * requestToDir, network="To", virtual_network="0",
- ordered="false", vnet_type="request";
+ vnet_type="request";
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -49,7 +49,7 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- MessageBuffer mandatoryQueue, ordered="false";
+ MessageBuffer mandatoryQueue;
State cur_state;
State getState(Address addr) {