diff options
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-dma.sm')
| -rw-r--r-- | src/mem/protocol/MESI_Two_Level-dma.sm | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm index ecda3bd03..73a1fa216 100644 --- a/src/mem/protocol/MESI_Two_Level-dma.sm +++ b/src/mem/protocol/MESI_Two_Level-dma.sm @@ -69,6 +69,7 @@ machine(MachineType:DMA, "DMA Controller") TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs"; Tick clockEdge(); + MachineID mapAddressToMachine(Addr addr, MachineType mtype); State getState(TBE tbe, Addr addr) { if (is_valid(tbe)) { @@ -138,7 +139,7 @@ machine(MachineType:DMA, "DMA Controller") out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Writeback_Control; } } @@ -151,7 +152,7 @@ machine(MachineType:DMA, "DMA Controller") out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Writeback_Control; } } |