diff options
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-dma.sm')
-rw-r--r-- | src/mem/protocol/MESI_Two_Level-dma.sm | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm index 37c5f982e..b9bb68cbd 100644 --- a/src/mem/protocol/MESI_Two_Level-dma.sm +++ b/src/mem/protocol/MESI_Two_Level-dma.sm @@ -106,7 +106,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, RequestMsg, request_latency) { out_msg.Addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; @@ -119,7 +119,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, RequestMsg, request_latency) { out_msg.Addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; |