diff options
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-dma.sm')
| -rw-r--r-- | src/mem/protocol/MESI_Two_Level-dma.sm | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm index 8032c0bec..f0301118c 100644 --- a/src/mem/protocol/MESI_Two_Level-dma.sm +++ b/src/mem/protocol/MESI_Two_Level-dma.sm @@ -32,8 +32,8 @@ machine(DMA, "DMA Controller") Cycles request_latency = 6 { - MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true"; - MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true"; + MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response"; + MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request"; state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; @@ -53,8 +53,8 @@ machine(DMA, "DMA Controller") void dataCallback(DataBlock); } - MessageBuffer mandatoryQueue, ordered="false", no_vector="true"; - State cur_state, no_vector="true"; + MessageBuffer mandatoryQueue, ordered="false"; + State cur_state; State getState(Address addr) { return cur_state; |