diff options
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
-rw-r--r-- | src/mem/protocol/MI_example-cache.sm | 40 |
1 files changed, 36 insertions, 4 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 0104e1aa2..84975ffd5 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -121,6 +121,17 @@ machine(L1Cache, "MI Example L1 Cache") } } + GenericMachineType getNondirectHitMachType(MachineID sender) { + if (machineIDToMachineType(sender) == MachineType:L1Cache) { + // + // NOTE direct local hits should not call this + // + return GenericMachineType:L1Cache_wCC; + } else { + return ConvertMachToGenericMach(machineIDToMachineType(sender)); + } + } + // NETWORK PORTS @@ -263,14 +274,35 @@ machine(L1Cache, "MI Example L1 Cache") action(r_load_hit, "r", desc="Notify sequencer the load completed.") { DEBUG_EXPR(getCacheEntry(address).DataBlk); - sequencer.readCallback(address, getCacheEntry(address).DataBlk); + sequencer.readCallback(address, + GenericMachineType:L1Cache, + getCacheEntry(address).DataBlk); + } + + action(rx_load_hit, "rx", desc="External load completed.") { + peek(responseNetwork_in, ResponseMsg) { + DEBUG_EXPR(getCacheEntry(address).DataBlk); + sequencer.readCallback(address, + getNondirectHitMachType(in_msg.Sender), + getCacheEntry(address).DataBlk); + } } action(s_store_hit, "s", desc="Notify sequencer that store completed.") { DEBUG_EXPR(getCacheEntry(address).DataBlk); - sequencer.writeCallback(address, getCacheEntry(address).DataBlk); + sequencer.writeCallback(address, + GenericMachineType:L1Cache, + getCacheEntry(address).DataBlk); } + action(sx_store_hit, "sx", desc="External store completed.") { + peek(responseNetwork_in, ResponseMsg) { + DEBUG_EXPR(getCacheEntry(address).DataBlk); + sequencer.writeCallback(address, + getNondirectHitMachType(in_msg.Sender), + getCacheEntry(address).DataBlk); + } + } action(u_writeDataToCache, "u", desc="Write data to the cache") { peek(responseNetwork_in, ResponseMsg) { @@ -342,14 +374,14 @@ machine(L1Cache, "MI Example L1 Cache") transition(IS, Data, M) { u_writeDataToCache; - r_load_hit; + rx_load_hit; w_deallocateTBE; n_popResponseQueue; } transition(IM, Data, M) { u_writeDataToCache; - s_store_hit; + sx_store_hit; w_deallocateTBE; n_popResponseQueue; } |