diff options
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
| -rw-r--r-- | src/mem/protocol/MI_example-cache.sm | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 84975ffd5..8232e93e1 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -273,7 +273,7 @@ machine(L1Cache, "MI Example L1 Cache") } action(r_load_hit, "r", desc="Notify sequencer the load completed.") { - DEBUG_EXPR(getCacheEntry(address).DataBlk); + DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk); sequencer.readCallback(address, GenericMachineType:L1Cache, getCacheEntry(address).DataBlk); @@ -281,7 +281,7 @@ machine(L1Cache, "MI Example L1 Cache") action(rx_load_hit, "rx", desc="External load completed.") { peek(responseNetwork_in, ResponseMsg) { - DEBUG_EXPR(getCacheEntry(address).DataBlk); + DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk); sequencer.readCallback(address, getNondirectHitMachType(in_msg.Sender), getCacheEntry(address).DataBlk); @@ -289,7 +289,7 @@ machine(L1Cache, "MI Example L1 Cache") } action(s_store_hit, "s", desc="Notify sequencer that store completed.") { - DEBUG_EXPR(getCacheEntry(address).DataBlk); + DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk); sequencer.writeCallback(address, GenericMachineType:L1Cache, getCacheEntry(address).DataBlk); @@ -297,7 +297,7 @@ machine(L1Cache, "MI Example L1 Cache") action(sx_store_hit, "sx", desc="External store completed.") { peek(responseNetwork_in, ResponseMsg) { - DEBUG_EXPR(getCacheEntry(address).DataBlk); + DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk); sequencer.writeCallback(address, getNondirectHitMachType(in_msg.Sender), getCacheEntry(address).DataBlk); |