diff options
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
-rw-r--r-- | src/mem/protocol/MI_example-cache.sm | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index cef89afda..afc415b5a 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -120,6 +120,26 @@ machine(L1Cache, "MI Example L1 Cache") } } + AccessPermission getAccessPermission(Address addr) { + TBE tbe := TBEs[addr]; + if(is_valid(tbe)) { + return L1Cache_State_to_permission(tbe.TBEState); + } + + Entry cache_entry := getCacheEntry(addr); + if(is_valid(cache_entry)) { + return L1Cache_State_to_permission(cache_entry.CacheState); + } + + return AccessPermission:NotPresent; + } + + void setAccessPermission(Entry cache_entry, Address addr, State state) { + if (is_valid(cache_entry)) { + cache_entry.changePermission(L1Cache_State_to_permission(state)); + } + } + GenericMachineType getNondirectHitMachType(MachineID sender) { if (machineIDToMachineType(sender) == MachineType:L1Cache) { // |