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-rw-r--r--src/mem/protocol/MI_example-cache.sm4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 91f060a38..e62317efa 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -30,8 +30,8 @@
machine(L1Cache, "MI Example L1 Cache")
: Sequencer * sequencer,
CacheMemory * cacheMemory,
- int cache_response_latency = 12,
- int issue_latency = 2,
+ Cycles cache_response_latency = 12,
+ Cycles issue_latency = 2,
bool send_evictions
{