diff options
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
-rw-r--r-- | src/mem/protocol/MI_example-cache.sm | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index f3b1600f9..334106615 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -352,6 +352,7 @@ machine(L1Cache, "MI Example L1 Cache") action(r_load_hit, "r", desc="Notify sequencer the load completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); + cacheMemory.setMRU(cache_entry); sequencer.readCallback(address, cache_entry.DataBlk, false); } @@ -359,6 +360,7 @@ machine(L1Cache, "MI Example L1 Cache") peek(responseNetwork_in, ResponseMsg) { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); + cacheMemory.setMRU(cache_entry); sequencer.readCallback(address, cache_entry.DataBlk, true, machineIDToMachineType(in_msg.Sender)); } @@ -367,6 +369,7 @@ machine(L1Cache, "MI Example L1 Cache") action(s_store_hit, "s", desc="Notify sequencer that store completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); + cacheMemory.setMRU(cache_entry); sequencer.writeCallback(address, cache_entry.DataBlk, false); } @@ -374,6 +377,7 @@ machine(L1Cache, "MI Example L1 Cache") peek(responseNetwork_in, ResponseMsg) { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); + cacheMemory.setMRU(cache_entry); sequencer.writeCallback(address, cache_entry.DataBlk, true, machineIDToMachineType(in_msg.Sender)); } |