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Diffstat (limited to 'src/mem/protocol/MI_example-dma.sm')
-rw-r--r--src/mem/protocol/MI_example-dma.sm9
1 files changed, 2 insertions, 7 deletions
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm
index 79c42e719..17060dd4d 100644
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/protocol/MI_example-dma.sm
@@ -1,6 +1,7 @@
machine(DMA, "DMA Controller")
-: int request_latency
+: DMASequencer * dma_sequencer,
+ int request_latency
{
MessageBuffer responseFromDir, network="From", virtual_network="4", ordered="true", no_vector="true";
@@ -19,13 +20,7 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- external_type(DMASequencer) {
- void ackCallback();
- void dataCallback(DataBlock);
- }
-
MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
- DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true";
State cur_state, no_vector="true";
State getState(Address addr) {