diff options
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_directory-L1cache.sm')
| -rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 8a2eee1e2..6c5d3a20f 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -51,6 +51,10 @@ machine(L1Cache, "Directory protocol") // a L2 bank -> this L1 MessageBuffer * responseToL1Cache, network="From", virtual_network="2", vnet_type="response"; + + MessageBuffer * triggerQueue; + + MessageBuffer * mandatoryQueue; { // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { @@ -134,8 +138,6 @@ machine(L1Cache, "Directory protocol") void set_tbe(TBE b); void unset_tbe(); - MessageBuffer mandatoryQueue, abstract_chip_ptr="true"; - TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; TimerTable useTimerTable; int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; @@ -254,8 +256,6 @@ machine(L1Cache, "Directory protocol") } } - MessageBuffer triggerQueue; - // ** OUT_PORTS ** out_port(requestNetwork_out, RequestMsg, requestFromL1Cache); |