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Diffstat (limited to 'src/mem/protocol/MOESI_CMP_directory-dma.sm')
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-dma.sm22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index d96276245..f79f0a535 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -120,15 +120,15 @@ machine(DMA, "DMA Controller")
if (dmaResponseQueue_in.isReady()) {
peek( dmaResponseQueue_in, ResponseMsg) {
if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
- trigger(Event:DMA_Ack, makeLineAddress(in_msg.Address),
- TBEs[makeLineAddress(in_msg.Address)]);
+ trigger(Event:DMA_Ack, makeLineAddress(in_msg.Addr),
+ TBEs[makeLineAddress(in_msg.Addr)]);
} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE ||
in_msg.Type == CoherenceResponseType:DATA) {
- trigger(Event:Data, makeLineAddress(in_msg.Address),
- TBEs[makeLineAddress(in_msg.Address)]);
+ trigger(Event:Data, makeLineAddress(in_msg.Addr),
+ TBEs[makeLineAddress(in_msg.Addr)]);
} else if (in_msg.Type == CoherenceResponseType:ACK) {
- trigger(Event:Inv_Ack, makeLineAddress(in_msg.Address),
- TBEs[makeLineAddress(in_msg.Address)]);
+ trigger(Event:Inv_Ack, makeLineAddress(in_msg.Addr),
+ TBEs[makeLineAddress(in_msg.Addr)]);
} else {
error("Invalid response type");
}
@@ -141,7 +141,7 @@ machine(DMA, "DMA Controller")
if (triggerQueue_in.isReady()) {
peek(triggerQueue_in, TriggerMsg) {
if (in_msg.Type == TriggerType:ALL_ACKS) {
- trigger(Event:All_Acks, in_msg.Address, TBEs[in_msg.Address]);
+ trigger(Event:All_Acks, in_msg.Addr, TBEs[in_msg.Addr]);
} else {
error("Unexpected message");
}
@@ -152,7 +152,7 @@ machine(DMA, "DMA Controller")
action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
peek(dmaRequestQueue_in, SequencerMsg) {
enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
- out_msg.Address := in_msg.PhysicalAddress;
+ out_msg.Addr := in_msg.PhysicalAddress;
out_msg.Type := CoherenceRequestType:DMA_READ;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Len := in_msg.Len;
@@ -167,7 +167,7 @@ machine(DMA, "DMA Controller")
action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
peek(dmaRequestQueue_in, SequencerMsg) {
enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
- out_msg.Address := in_msg.PhysicalAddress;
+ out_msg.Addr := in_msg.PhysicalAddress;
out_msg.Type := CoherenceRequestType:DMA_WRITE;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Len := in_msg.Len;
@@ -187,7 +187,7 @@ machine(DMA, "DMA Controller")
assert(is_valid(tbe));
if (tbe.NumAcks == 0) {
enqueue(triggerQueue_out, TriggerMsg) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := TriggerType:ALL_ACKS;
}
}
@@ -202,7 +202,7 @@ machine(DMA, "DMA Controller")
action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") {
enqueue(respToDirectory_out, ResponseMsg, latency=response_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.Sender := machineID;