diff options
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_token-L1cache.sm')
| -rw-r--r-- | src/mem/protocol/MOESI_CMP_token-L1cache.sm | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index c5a7cd940..230adfc4b 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -1282,12 +1282,22 @@ machine(L1Cache, "Token protocol") } } + action(h_load_hit, "hd", desc="Notify sequencer the load completed.") { + assert(is_valid(cache_entry)); + DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n", + address, cache_entry.DataBlk); - action(h_load_hit, "h", desc="Notify sequencer the load completed.") { + L1Dcache.setMRU(cache_entry); + sequencer.readCallback(address, cache_entry.DataBlk, false, + MachineType:L1Cache); + } + + action(h_ifetch_hit, "hi", desc="Notify sequencer the load completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n", address, cache_entry.DataBlk); + L1Icache.setMRU(cache_entry); sequencer.readCallback(address, cache_entry.DataBlk, false, MachineType:L1Cache); } @@ -1297,6 +1307,8 @@ machine(L1Cache, "Token protocol") DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n", address, cache_entry.DataBlk); peek(responseNetwork_in, ResponseMsg) { + L1Icache.setMRU(address); + L1Dcache.setMRU(address); sequencer.readCallback(address, cache_entry.DataBlk, isExternalHit(address, in_msg.Sender), machineIDToMachineType(in_msg.Sender)); @@ -1308,6 +1320,7 @@ machine(L1Cache, "Token protocol") DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n", address, cache_entry.DataBlk); + L1Dcache.setMRU(cache_entry); sequencer.writeCallback(address, cache_entry.DataBlk, false, MachineType:L1Cache); cache_entry.Dirty := true; @@ -1319,6 +1332,8 @@ machine(L1Cache, "Token protocol") DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n", address, cache_entry.DataBlk); peek(responseNetwork_in, ResponseMsg) { + L1Icache.setMRU(address); + L1Dcache.setMRU(address); sequencer.writeCallback(address, cache_entry.DataBlk, isExternalHit(address, in_msg.Sender), machineIDToMachineType(in_msg.Sender)); @@ -1700,7 +1715,7 @@ machine(L1Cache, "Token protocol") } transition({S, SM, S_L, SM_L}, Ifetch) { - h_load_hit; + h_ifetch_hit; uu_profileInstHit; k_popMandatoryQueue; } @@ -1782,7 +1797,7 @@ machine(L1Cache, "Token protocol") // Transitions from Owned transition({O, OM}, Ifetch) { - h_load_hit; + h_ifetch_hit; uu_profileInstHit; k_popMandatoryQueue; } @@ -1872,7 +1887,7 @@ machine(L1Cache, "Token protocol") // Transitions from Modified transition({MM, MM_W}, Ifetch) { - h_load_hit; + h_ifetch_hit; uu_profileInstHit; k_popMandatoryQueue; } @@ -1947,7 +1962,7 @@ machine(L1Cache, "Token protocol") // Transitions from Dirty Exclusive transition({M, M_W}, Ifetch) { - h_load_hit; + h_ifetch_hit; uu_profileInstHit; k_popMandatoryQueue; } |