diff options
Diffstat (limited to 'src/mem/protocol/MOESI_hammer-cache.sm')
-rw-r--r-- | src/mem/protocol/MOESI_hammer-cache.sm | 61 |
1 files changed, 22 insertions, 39 deletions
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 9592e3881..05d74038b 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -54,31 +54,31 @@ machine(L1Cache, "AMD Hammer-like protocol") // STATES - enumeration(State, desc="Cache states", default="L1Cache_State_I") { + state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states - I, desc="Idle"; - S, desc="Shared"; - O, desc="Owned"; - M, desc="Modified (dirty)"; - MM, desc="Modified (dirty and locally modified)"; + I, AccessPermission:Invalid, desc="Idle"; + S, AccessPermission:Read_Only, desc="Shared"; + O, AccessPermission:Read_Only, desc="Owned"; + M, AccessPermission:Read_Only, desc="Modified (dirty)"; + MM, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)"; // Transient States - IM, "IM", desc="Issued GetX"; - SM, "SM", desc="Issued GetX, we still have an old copy of the line"; - OM, "OM", desc="Issued GetX, received data"; - ISM, "ISM", desc="Issued GetX, received data, waiting for all acks"; - M_W, "M^W", desc="Issued GetS, received exclusive data"; - MM_W, "MM^W", desc="Issued GetX, received exclusive data"; - IS, "IS", desc="Issued GetS"; - SS, "SS", desc="Issued GetS, received data, waiting for all acks"; - OI, "OI", desc="Issued PutO, waiting for ack"; - MI, "MI", desc="Issued PutX, waiting for ack"; - II, "II", desc="Issued PutX/O, saw Other_GETS or Other_GETX, waiting for ack"; - IT, "IT", desc="Invalid block transferring to L1"; - ST, "ST", desc="S block transferring to L1"; - OT, "OT", desc="O block transferring to L1"; - MT, "MT", desc="M block transferring to L1"; - MMT, "MMT", desc="MM block transferring to L1"; + IM, AccessPermission:Busy, "IM", desc="Issued GetX"; + SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have a valid copy of the line"; + OM, AccessPermission:Read_Only, "OM", desc="Issued GetX, received data"; + ISM, AccessPermission:Read_Only, "ISM", desc="Issued GetX, received valid data, waiting for all acks"; + M_W, AccessPermission:Read_Only, "M^W", desc="Issued GetS, received exclusive data"; + MM_W, AccessPermission:Read_Write, "MM^W", desc="Issued GetX, received exclusive data"; + IS, AccessPermission:Busy, "IS", desc="Issued GetS"; + SS, AccessPermission:Read_Only, "SS", desc="Issued GetS, received data, waiting for all acks"; + OI, AccessPermission:Busy, "OI", desc="Issued PutO, waiting for ack"; + MI, AccessPermission:Busy, "MI", desc="Issued PutX, waiting for ack"; + II, AccessPermission:Busy, "II", desc="Issued PutX/O, saw Other_GETS or Other_GETX, waiting for ack"; + IT, AccessPermission:Busy, "IT", desc="Invalid block transferring to L1"; + ST, AccessPermission:Busy, "ST", desc="S block transferring to L1"; + OT, AccessPermission:Busy, "OT", desc="O block transferring to L1"; + MT, AccessPermission:Busy, "MT", desc="M block transferring to L1"; + MMT, AccessPermission:Busy, "MMT", desc="MM block transferring to L1"; } // EVENTS @@ -209,23 +209,6 @@ machine(L1Cache, "AMD Hammer-like protocol") if (is_valid(cache_entry)) { cache_entry.CacheState := state; - - // Set permission - if ((state == State:MM) || - (state == State:MM_W)) { - cache_entry.changePermission(AccessPermission:Read_Write); - } else if (state == State:S || - state == State:O || - state == State:M || - state == State:M_W || - state == State:SM || - state == State:ISM || - state == State:OM || - state == State:SS) { - cache_entry.changePermission(AccessPermission:Read_Only); - } else { - cache_entry.changePermission(AccessPermission:Invalid); - } } } |