diff options
Diffstat (limited to 'src/mem/protocol/MOESI_hammer-cache.sm')
-rw-r--r-- | src/mem/protocol/MOESI_hammer-cache.sm | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index de502e118..badbe1d8b 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -205,18 +205,34 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") return L1Icache_entry; } - DataBlock getDataBlock(Address addr), return_by_ref="yes" { + void functionalRead(Address addr, Packet *pkt) { Entry cache_entry := getCacheEntry(addr); if(is_valid(cache_entry)) { - return cache_entry.DataBlk; + testAndRead(addr, cache_entry.DataBlk, pkt); + } else { + TBE tbe := TBEs[addr]; + if(is_valid(tbe)) { + testAndRead(addr, tbe.DataBlk, pkt); + } else { + error("Missing data block"); + } } + } - TBE tbe := TBEs[addr]; - if(is_valid(tbe)) { - return tbe.DataBlk; + int functionalWrite(Address addr, Packet *pkt) { + int num_functional_writes := 0; + + Entry cache_entry := getCacheEntry(addr); + if(is_valid(cache_entry)) { + num_functional_writes := num_functional_writes + + testAndWrite(addr, cache_entry.DataBlk, pkt); + return num_functional_writes; } - error("Missing data block"); + TBE tbe := TBEs[addr]; + num_functional_writes := num_functional_writes + + testAndWrite(addr, tbe.DataBlk, pkt); + return num_functional_writes; } Entry getL2CacheEntry(Address address), return_by_pointer="yes" { |