diff options
Diffstat (limited to 'src/mem/protocol/MOESI_hammer-cache.sm')
| -rw-r--r-- | src/mem/protocol/MOESI_hammer-cache.sm | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 21e8b7309..d5539e021 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -174,10 +174,10 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; @@ -187,10 +187,10 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") void set_tbe(TBE b); void unset_tbe(); void wakeUpAllBuffers(); - void wakeUpBuffers(Address a); + void wakeUpBuffers(Addr a); Cycles curCycle(); - Entry getCacheEntry(Address address), return_by_pointer="yes" { + Entry getCacheEntry(Addr address), return_by_pointer="yes" { Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address)); if(is_valid(L2cache_entry)) { return L2cache_entry; @@ -205,7 +205,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") return L1Icache_entry; } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { Entry cache_entry := getCacheEntry(addr); if(is_valid(cache_entry)) { testAndRead(addr, cache_entry.DataBlk, pkt); @@ -219,7 +219,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; Entry cache_entry := getCacheEntry(addr); @@ -235,22 +235,22 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") return num_functional_writes; } - Entry getL2CacheEntry(Address address), return_by_pointer="yes" { + Entry getL2CacheEntry(Addr address), return_by_pointer="yes" { Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address)); return L2cache_entry; } - Entry getL1DCacheEntry(Address address), return_by_pointer="yes" { + Entry getL1DCacheEntry(Addr address), return_by_pointer="yes" { Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(address)); return L1Dcache_entry; } - Entry getL1ICacheEntry(Address address), return_by_pointer="yes" { + Entry getL1ICacheEntry(Addr address), return_by_pointer="yes" { Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(address)); return L1Icache_entry; } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(TBE tbe, Entry cache_entry, Addr addr) { if(is_valid(tbe)) { return tbe.TBEState; } else if (is_valid(cache_entry)) { @@ -259,7 +259,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") return State:I; } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false); assert((L1Icache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false); assert((L1Dcache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false); @@ -273,7 +273,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { return L1Cache_State_to_permission(tbe.TBEState); @@ -287,7 +287,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") return AccessPermission:NotPresent; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L1Cache_State_to_permission(state)); } @@ -448,7 +448,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") if (L2cache.cacheAvail(in_msg.LineAddress)) { trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe); } else { - Address l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress); + Addr l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress); trigger(Event:L2_Replacement, l2_victim_addr, getL2CacheEntry(l2_victim_addr), @@ -471,7 +471,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } } else { // No room in the L1, so we need to make room - Address l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress); + Addr l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress); if (L2cache.cacheAvail(l1i_victim_addr)) { // The L2 has room, so we move the line from the L1 to the L2 trigger(Event:L1_to_L2, @@ -479,7 +479,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") getL1ICacheEntry(l1i_victim_addr), TBEs[l1i_victim_addr]); } else { - Address l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr); + Addr l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr); // The L2 does not have room, so we replace a line from the L2 trigger(Event:L2_Replacement, l2_victim_addr, @@ -506,7 +506,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") if (L2cache.cacheAvail(in_msg.LineAddress)) { trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe); } else { - Address l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress); + Addr l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress); trigger(Event:L2_Replacement, l2_victim_addr, getL2CacheEntry(l2_victim_addr), @@ -528,7 +528,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } } else { // No room in the L1, so we need to make room - Address l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress); + Addr l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress); if (L2cache.cacheAvail(l1d_victim_addr)) { // The L2 has room, so we move the line from the L1 to the L2 trigger(Event:L1_to_L2, @@ -536,7 +536,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") getL1DCacheEntry(l1d_victim_addr), TBEs[l1d_victim_addr]); } else { - Address l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr); + Addr l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr); // The L2 does not have room, so we replace a line from the L2 trigger(Event:L2_Replacement, l2_victim_addr, |