diff options
Diffstat (limited to 'src/mem/protocol/RubySlicc_Exports.sm')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Exports.sm | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index 1d591482d..b643a3da1 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -35,7 +35,7 @@ external_type(uint32_t, primitive="yes"); external_type(uint64, primitive="yes"); external_type(PacketPtr, primitive="yes"); external_type(Packet, primitive="yes"); -external_type(Address); +external_type(Addr, primitive="yes"); external_type(Cycles, primitive="yes", default="Cycles(0)"); structure(DataBlock, external = "yes", desc="..."){ @@ -43,8 +43,8 @@ structure(DataBlock, external = "yes", desc="..."){ void copyPartial(DataBlock, int, int); } -bool testAndRead(Address addr, DataBlock datablk, Packet *pkt); -bool testAndWrite(Address addr, DataBlock datablk, Packet *pkt); +bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt); +bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt); // AccessPermission // The following five states define the access permission of all memory blocks. @@ -215,10 +215,10 @@ enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") { // CacheMsg structure(SequencerMsg, desc="...", interface="Message") { - Address LineAddress, desc="Line address for this request"; - Address PhysicalAddress, desc="Physical address for this request"; + Addr LineAddress, desc="Line address for this request"; + Addr PhysicalAddress, desc="Physical address for this request"; SequencerRequestType Type, desc="Type of request (LD, ST, etc)"; - Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; + Addr ProgramCounter, desc="Program counter of the instruction that caused the miss"; RubyAccessMode AccessMode, desc="user/supervisor access type"; DataBlock DataBlk, desc="Data"; int Len, desc="size in bytes of access"; |