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Diffstat (limited to 'src/mem/protocol/RubySlicc_Types.sm')
-rw-r--r--src/mem/protocol/RubySlicc_Types.sm10
1 files changed, 4 insertions, 6 deletions
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index c94020792..acd86a8fe 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -37,6 +37,7 @@
external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes");
external_type(OutPort, primitive="yes");
+external_type(Scalar, primitive="yes");
structure(InPort, external = "yes", primitive="yes") {
bool isReady();
@@ -148,15 +149,12 @@ structure (CacheMemory, external = "yes") {
void deallocate(Address);
AbstractCacheEntry lookup(Address);
bool isTagPresent(Address);
- void profileMiss(RubyRequest);
-
- void profileGenericRequest(GenericRequestType,
- RubyAccessMode,
- PrefetchBit);
-
void setMRU(Address);
void recordRequestType(CacheRequestType);
bool checkResourceAvailable(CacheResourceType, Address);
+
+ Scalar demand_misses;
+ Scalar demand_hits;
}
structure (WireBuffer, inport="yes", outport="yes", external = "yes") {