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Diffstat (limited to 'src/mem/protocol/RubySlicc_Types.sm')
-rw-r--r--src/mem/protocol/RubySlicc_Types.sm12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index d9c3077a2..118cbc2f0 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -109,6 +109,16 @@ structure (Sequencer, external = "yes") {
void profileNack(Address, int, int, uint64);
}
+structure(RubyRequest, desc="...", interface="Message", external="yes") {
+ Address LineAddress, desc="Line address for this request";
+ Address PhysicalAddress, desc="Physical address for this request";
+ RubyRequestType Type, desc="Type of request (LD, ST, etc)";
+ Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
+ int Size, desc="size in bytes of access";
+ PrefetchBit Prefetch, desc="Is this a prefetch request";
+}
+
external_type(AbstractEntry, primitive="yes");
structure (DirectoryMemory, external = "yes") {
@@ -126,7 +136,7 @@ structure (CacheMemory, external = "yes") {
void deallocate(Address);
AbstractCacheEntry lookup(Address);
bool isTagPresent(Address);
- void profileMiss(CacheMsg);
+ void profileMiss(RubyRequest);
void profileGenericRequest(GenericRequestType,
RubyAccessMode,