2 files changed, 25 insertions, 1 deletions
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index ca80047f7..ef752c604 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -138,6 +138,7 @@ enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
 }
 
 enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
+  Default,    desc="Replace this with access_types passed to the DMA Ruby object";
   LD,          desc="Load";
   ST,          desc="Store";
   NULL,        desc="Invalid request type";
@@ -176,6 +177,25 @@ enumeration(GenericRequestType, desc="...", default="GenericRequestType_NULL") {
   NULL,        desc="null request type";
 }
 
+enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
+  DataArrayRead,    desc="Read access to the cache's data array";
+  DataArrayWrite,   desc="Write access to the cache's data array";
+  TagArrayRead,     desc="Read access to the cache's tag array";
+  TagArrayWrite,    desc="Write access to the cache's tag array";
+}
+
+enumeration(DirectoryRequestType, desc="...", default="DirectoryRequestType_NULL") {
+  Default,    desc="Replace this with access_types passed to the Directory Ruby object";
+}
+
+enumeration(DMASequencerRequestType, desc="...", default="DMASequencerRequestType_NULL") {
+  Default,    desc="Replace this with access_types passed to the DMA Ruby object";
+}
+
+enumeration(MemoryControlRequestType, desc="...", default="MemoryControlRequestType_NULL") {
+  Default,    desc="Replace this with access_types passed to the DMA Ruby object";
+}
+
 enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL") {
   L1Cache,     desc="L1 Cache Mach";
   L2Cache,     desc="L2 Cache Mach";
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index 3b90dab20..436b39273 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -108,6 +108,7 @@ structure (Sequencer, external = "yes") {
   void checkCoherence(Address);
   void profileNack(Address, int, int, uint64);
   void evictionCallback(Address);
+  void recordRequestType(SequencerRequestType);
 }
 
 structure(RubyRequest, desc="...", interface="Message", external="yes") {
@@ -130,6 +131,7 @@ structure (DirectoryMemory, external = "yes") {
   AbstractEntry lookup(Address);
   bool isPresent(Address);
   void invalidateBlock(Address);
+  void recordRequestType(DirectoryRequestType);
 }
 
 structure(AbstractCacheEntry, primitive="yes", external = "yes") {
@@ -151,6 +153,7 @@ structure (CacheMemory, external = "yes") {
                              PrefetchBit);
 
   void setMRU(Address);
+  void recordRequestType(CacheRequestType);
 }
 
 structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
@@ -158,12 +161,13 @@ structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
 }
 
 structure (MemoryControl, inport="yes", outport="yes", external = "yes") {
-
+  void recordRequestType(CacheRequestType);
 }
 
 structure (DMASequencer, external = "yes") {
   void ackCallback();
   void dataCallback(DataBlock);
+  void recordRequestType(CacheRequestType);
 }
 
 structure (TimerTable, inport="yes", external = "yes") {