summaryrefslogtreecommitdiff
path: root/src/mem/protocol
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/protocol')
-rw-r--r--src/mem/protocol/MESI_Three_Level-L0cache.sm6
-rw-r--r--src/mem/protocol/MESI_Two_Level-L1cache.sm9
-rw-r--r--src/mem/protocol/MESI_Two_Level-dir.sm4
-rw-r--r--src/mem/protocol/MESI_Two_Level-dma.sm2
-rw-r--r--src/mem/protocol/MI_example-cache.sm5
-rw-r--r--src/mem/protocol/MI_example-dir.sm3
-rw-r--r--src/mem/protocol/MI_example-dma.sm5
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-L1cache.sm8
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-L2cache.sm3
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-dir.sm3
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-dma.sm4
-rw-r--r--src/mem/protocol/MOESI_CMP_token-L1cache.sm4
-rw-r--r--src/mem/protocol/MOESI_CMP_token-dir.sm3
-rw-r--r--src/mem/protocol/MOESI_CMP_token-dma.sm5
-rw-r--r--src/mem/protocol/MOESI_hammer-cache.sm12
-rw-r--r--src/mem/protocol/MOESI_hammer-dir.sm6
-rw-r--r--src/mem/protocol/MOESI_hammer-dma.sm2
-rw-r--r--src/mem/protocol/Network_test-cache.sm5
18 files changed, 40 insertions, 49 deletions
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
index 8e44766ea..4a0766ce8 100644
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -39,10 +39,10 @@ machine(L0Cache, "MESI Directory L0 Cache")
// To this node's L0 cache FROM the network
MessageBuffer * bufferFromL1, network="From";
-{
- // Message queue between this controller and the processor
- MessageBuffer mandatoryQueue;
+ // Message queue between this controller and the processor
+ MessageBuffer * mandatoryQueue;
+{
// STATES
state_declaration(State, desc="Cache states", default="L0Cache_State_I") {
// Base states
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index 184f735c7..8033e5983 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -61,10 +61,13 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
// a L2 bank -> this L1
MessageBuffer * responseToL1Cache, network="From", virtual_network="1",
vnet_type="response";
-{
+
// Request Buffer for prefetches
- MessageBuffer optionalQueue;
+ MessageBuffer * optionalQueue;
+ // Buffer for requests generated by the processor core.
+ MessageBuffer * mandatoryQueue;
+{
// STATES
state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
// Base states
@@ -151,8 +154,6 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
- MessageBuffer mandatoryQueue;
-
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
void set_cache_entry(AbstractCacheEntry a);
diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm
index 22aabee4e..7484d001c 100644
--- a/src/mem/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm
@@ -37,6 +37,8 @@ machine(Directory, "MESI Two Level directory protocol")
vnet_type="response";
MessageBuffer * responseFromDir, network="To", virtual_network="1",
vnet_type="response";
+
+ MessageBuffer * responseFromMemory;
{
// STATES
state_declaration(State, desc="Directory states", default="Directory_State_I") {
@@ -182,8 +184,6 @@ machine(Directory, "MESI Two Level directory protocol")
(type == CoherenceRequestType:GETX);
}
- MessageBuffer responseFromMemory;
-
// ** OUT_PORTS **
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm
index 0caff177d..cbd32cd44 100644
--- a/src/mem/protocol/MESI_Two_Level-dma.sm
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm
@@ -35,6 +35,7 @@ machine(DMA, "DMA Controller")
vnet_type="response";
MessageBuffer * requestToDir, network="To", virtual_network="0",
vnet_type="request";
+ MessageBuffer * mandatoryQueue;
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -49,7 +50,6 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- MessageBuffer mandatoryQueue;
State cur_state;
State getState(Addr addr) {
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 3380cd7e6..f3b1600f9 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -44,6 +44,8 @@ machine(L1Cache, "MI Example L1 Cache")
vnet_type="forward";
MessageBuffer * responseToCache, network="From", virtual_network="4",
vnet_type="response";
+
+ MessageBuffer * mandatoryQueue;
{
// STATES
state_declaration(State, desc="Cache states") {
@@ -76,9 +78,6 @@ machine(L1Cache, "MI Example L1 Cache")
}
// STRUCTURE DEFINITIONS
-
- MessageBuffer mandatoryQueue;
-
// CacheEntry
structure(Entry, desc="...", interface="AbstractCacheEntry") {
State CacheState, desc="cache state";
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index a22691bda..bb4373901 100644
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -43,6 +43,7 @@ machine(Directory, "Directory protocol")
vnet_type="request";
MessageBuffer * dmaRequestToDir, network="From", virtual_network="0",
vnet_type="request";
+ MessageBuffer * responseFromMemory;
{
// STATES
state_declaration(State, desc="Directory states", default="Directory_State_I") {
@@ -195,8 +196,6 @@ machine(Directory, "Directory protocol")
return num_functional_writes;
}
- MessageBuffer responseFromMemory;
-
// ** OUT_PORTS **
out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm
index 4ae546d64..ce7b44630 100644
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/protocol/MI_example-dma.sm
@@ -35,6 +35,7 @@ machine(DMA, "DMA Controller")
vnet_type="response";
MessageBuffer * requestToDir, network="To", virtual_network="0",
vnet_type="request";
+ MessageBuffer * mandatoryQueue;
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -49,14 +50,14 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- MessageBuffer mandatoryQueue;
State cur_state;
State getState(Addr addr) {
return cur_state;
}
+
void setState(Addr addr, State state) {
- cur_state := state;
+ cur_state := state;
}
AccessPermission getAccessPermission(Addr addr) {
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index 8a2eee1e2..6c5d3a20f 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -51,6 +51,10 @@ machine(L1Cache, "Directory protocol")
// a L2 bank -> this L1
MessageBuffer * responseToL1Cache, network="From", virtual_network="2",
vnet_type="response";
+
+ MessageBuffer * triggerQueue;
+
+ MessageBuffer * mandatoryQueue;
{
// STATES
state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
@@ -134,8 +138,6 @@ machine(L1Cache, "Directory protocol")
void set_tbe(TBE b);
void unset_tbe();
- MessageBuffer mandatoryQueue, abstract_chip_ptr="true";
-
TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
TimerTable useTimerTable;
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
@@ -254,8 +256,6 @@ machine(L1Cache, "Directory protocol")
}
}
- MessageBuffer triggerQueue;
-
// ** OUT_PORTS **
out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
index 38c6e9f9b..0b288709e 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -48,6 +48,7 @@ machine(L2Cache, "Token protocol")
MessageBuffer * responseToL2Cache, network="From", virtual_network="2",
vnet_type="response"; // a local L1 || mod-directory -> this L2 bank
+ MessageBuffer * triggerQueue;
{
// STATES
state_declaration(State, desc="L2 Cache states", default="L2Cache_State_I") {
@@ -565,8 +566,6 @@ machine(L2Cache, "Token protocol")
return num_functional_writes;
}
- MessageBuffer triggerQueue;
-
out_port(globalRequestNetwork_out, RequestMsg, GlobalRequestFromL2Cache);
out_port(localRequestNetwork_out, RequestMsg, L1RequestFromL2Cache);
out_port(responseNetwork_out, ResponseMsg, responseFromL2Cache);
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
index dcd37cc33..6ee7cd260 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -42,6 +42,7 @@ machine(Directory, "Directory protocol")
MessageBuffer * responseFromDir, network="To", virtual_network="2",
vnet_type="response"; // Dir -> mod-L2 bank
+ MessageBuffer * responseFromMemory;
{
// STATES
state_declaration(State, desc="Directory states", default="Directory_State_I") {
@@ -220,8 +221,6 @@ machine(Directory, "Directory protocol")
return false;
}
- MessageBuffer responseFromMemory;
-
// ** OUT_PORTS **
out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index e9931f25b..10fc94abe 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -40,6 +40,8 @@ machine(DMA, "DMA Controller")
MessageBuffer * respToDir, network="To", virtual_network="2",
vnet_type="dmaresponse";
+ MessageBuffer * mandatoryQueue;
+ MessageBuffer * triggerQueue;
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -69,8 +71,6 @@ machine(DMA, "DMA Controller")
bool isPresent(Addr);
}
- MessageBuffer mandatoryQueue;
- MessageBuffer triggerQueue;
TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
State cur_state;
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index af6e4c0d5..c5a7cd940 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -61,7 +61,6 @@ machine(L1Cache, "Token protocol")
MessageBuffer * requestFromL1Cache, network="To", virtual_network="1",
vnet_type="request";
-
// To this node's L1 cache FROM the network
// a L2 bank -> this L1
@@ -73,6 +72,7 @@ machine(L1Cache, "Token protocol")
MessageBuffer * requestToL1Cache, network="From", virtual_network="1",
vnet_type="request";
+ MessageBuffer * mandatoryQueue;
{
// STATES
state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
@@ -194,8 +194,6 @@ machine(L1Cache, "Token protocol")
TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
- MessageBuffer mandatoryQueue, abstract_chip_ptr="true";
-
bool starving, default="false";
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
index fdef75181..ffef01eb0 100644
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -61,6 +61,7 @@ machine(Directory, "Token protocol")
MessageBuffer * dmaRequestToDir, network="From", virtual_network="0",
vnet_type="request";
+ MessageBuffer * responseFromMemory;
{
// STATES
state_declaration(State, desc="Directory states", default="Directory_State_O") {
@@ -266,8 +267,6 @@ machine(Directory, "Token protocol")
return num_functional_writes;
}
- MessageBuffer responseFromMemory;
-
// ** OUT_PORTS **
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
out_port(persistentNetwork_out, PersistentMsg, persistentFromDir);
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
index 56cfb2012..4bb80d4ba 100644
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -37,6 +37,7 @@ machine(DMA, "DMA Controller")
MessageBuffer * reqToDirectory, network="To", virtual_network="0",
vnet_type="request";
+ MessageBuffer * mandatoryQueue;
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -51,14 +52,14 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- MessageBuffer mandatoryQueue;
State cur_state;
State getState(Addr addr) {
return cur_state;
}
+
void setState(Addr addr, State state) {
- cur_state := state;
+ cur_state := state;
}
AccessPermission getAccessPermission(Addr addr) {
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index d5539e021..303bf1784 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -56,6 +56,10 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
vnet_type="forward";
MessageBuffer * responseToCache, network="From", virtual_network="4",
vnet_type="response";
+
+ MessageBuffer * mandatoryQueue;
+
+ MessageBuffer * triggerQueue;
{
// STATES
state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
@@ -139,12 +143,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
Block_Ack, desc="the directory is blocked and ready for the flush";
}
- // TYPES
-
// STRUCTURE DEFINITIONS
-
- MessageBuffer mandatoryQueue;
-
// CacheEntry
structure(Entry, desc="...", interface="AbstractCacheEntry") {
State CacheState, desc="cache state";
@@ -320,10 +319,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
return cache_entry.AtomicAccessed;
}
- MessageBuffer triggerQueue;
-
// ** OUT_PORTS **
-
out_port(requestNetwork_out, RequestMsg, requestFromCache);
out_port(responseNetwork_out, ResponseMsg, responseFromCache);
out_port(unblockNetwork_out, ResponseMsg, unblockFromCache);
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 27794a3bd..4948a8108 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -64,6 +64,9 @@ machine(Directory, "AMD Hammer-like protocol")
MessageBuffer * dmaRequestToDir, network="From", virtual_network="0",
vnet_type="request";
+
+ MessageBuffer * triggerQueue;
+ MessageBuffer * responseFromMemory;
{
// STATES
state_declaration(State, desc="Directory states", default="Directory_State_E") {
@@ -300,9 +303,6 @@ machine(Directory, "AMD Hammer-like protocol")
}
}
- MessageBuffer triggerQueue;
- MessageBuffer responseFromMemory;
-
// ** OUT_PORTS **
out_port(requestQueue_out, ResponseMsg, requestToDir); // For recycling requests
out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm
index 72125d157..4691e2490 100644
--- a/src/mem/protocol/MOESI_hammer-dma.sm
+++ b/src/mem/protocol/MOESI_hammer-dma.sm
@@ -35,6 +35,7 @@ machine(DMA, "DMA Controller")
vnet_type="response";
MessageBuffer * requestToDir, network="To", virtual_network="0",
vnet_type="request";
+ MessageBuffer * mandatoryQueue;
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -49,7 +50,6 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- MessageBuffer mandatoryQueue;
State cur_state;
State getState(Addr addr) {
diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm
index 43331d8f2..82829a6ea 100644
--- a/src/mem/protocol/Network_test-cache.sm
+++ b/src/mem/protocol/Network_test-cache.sm
@@ -42,6 +42,8 @@ machine(L1Cache, "Network_test L1 Cache")
vnet_type = "forward";
MessageBuffer * responseFromCache, network="To", virtual_network="2",
vnet_type = "response";
+
+ MessageBuffer * mandatoryQueue;
{
// STATES
state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
@@ -57,11 +59,8 @@ machine(L1Cache, "Network_test L1 Cache")
}
// STRUCTURE DEFINITIONS
-
- MessageBuffer mandatoryQueue;
DataBlock dummyData;
-
// CacheEntry
structure(Entry, desc="...", interface="AbstractCacheEntry") {
State CacheState, desc="cache state";
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 10:10:34 +0000