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-rw-r--r--src/mem/protocol/MESI_CMP_directory-L1cache.sm2
-rw-r--r--src/mem/protocol/MESI_CMP_directory-L2cache.sm2
-rw-r--r--src/mem/protocol/MESI_CMP_directory-dir.sm2
-rw-r--r--src/mem/protocol/MESI_CMP_directory-dma.sm2
-rw-r--r--src/mem/protocol/MI_example-cache.sm2
-rw-r--r--src/mem/protocol/MI_example-dir.sm2
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-L1cache.sm2
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-L2cache.sm4
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-dir.sm2
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-dma.sm4
-rw-r--r--src/mem/protocol/MOESI_CMP_token-L1cache.sm4
-rw-r--r--src/mem/protocol/MOESI_CMP_token-L2cache.sm4
-rw-r--r--src/mem/protocol/MOESI_CMP_token-dir.sm4
-rw-r--r--src/mem/protocol/MOESI_CMP_token-dma.sm2
-rw-r--r--src/mem/protocol/MOESI_hammer-cache.sm2
-rw-r--r--src/mem/protocol/MOESI_hammer-dir.sm2
-rw-r--r--src/mem/protocol/RubySlicc_Exports.sm2
-rw-r--r--src/mem/protocol/RubySlicc_Types.sm25
18 files changed, 32 insertions, 37 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
index ecd8c9681..ab37a1bd8 100644
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
@@ -119,7 +119,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
int pendingAcks, default="0", desc="number of pending acks";
}
- external_type(TBETable) {
+ structure(TBETable, external="yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
index c30e42e69..42fe0823f 100644
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
@@ -145,7 +145,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
int pendingAcks, desc="number of pending acks for invalidates during writeback";
}
- external_type(TBETable) {
+ structure(TBETable, external="yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm
index 46c14bc0f..c47df9433 100644
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm
@@ -95,7 +95,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
int Len, desc="...";
}
- external_type(TBETable) {
+ structure(TBETable, external="yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/MESI_CMP_directory-dma.sm b/src/mem/protocol/MESI_CMP_directory-dma.sm
index 3fab439c6..da8b94b7c 100644
--- a/src/mem/protocol/MESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dma.sm
@@ -20,7 +20,7 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- external_type(DMASequencer) {
+ structure(DMASequencer, external="yes") {
void ackCallback();
void dataCallback(DataBlock);
}
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 26572770c..c992e4a68 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -61,7 +61,7 @@ machine(L1Cache, "MI Example L1 Cache")
DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
}
- external_type(TBETable) {
+ structure(TBETable, external="yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index d4ba3829d..71e022df5 100644
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -66,7 +66,7 @@ machine(Directory, "Directory protocol")
MachineID DmaRequestor, desc="DMA requestor";
}
- external_type(TBETable) {
+ structure(TBETable, external="yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index 50df2e52a..78641d014 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -127,7 +127,7 @@ machine(L1Cache, "Directory protocol")
int NumPendingMsgs, default="0", desc="Number of acks/data messages that this processor is waiting for";
}
- external_type(TBETable) {
+ structure(TBETable, external ="yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
index cdc91c292..059fcac71 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -203,14 +203,14 @@ machine(L2Cache, "Token protocol")
MachineID Fwd_GetX_ID, desc="ID of the L1 cache to forward the block to once we get a response";
}
- external_type(TBETable) {
+ structure(TBETable, external = "yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
bool isPresent(Address);
}
- external_type(PerfectCacheMemory) {
+ structure(PerfectCacheMemory, external = "yes") {
void allocate(Address);
void deallocate(Address);
DirEntry lookup(Address);
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
index 55afa7161..42d46e501 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -109,7 +109,7 @@ machine(Directory, "Directory protocol")
MachineID Requestor, desc="original requestor";
}
- external_type(TBETable) {
+ structure(TBETable, external = "yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index 43503ee25..30a311f67 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -34,12 +34,12 @@ machine(DMA, "DMA Controller")
DataBlock DataBlk, desc="Data";
}
- external_type(DMASequencer) {
+ structure(DMASequencer, external = "yes") {
void ackCallback();
void dataCallback(DataBlock);
}
- external_type(TBETable) {
+ structure(TBETable, external = "yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index edaf5f8ae..7683b485f 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -153,14 +153,14 @@ machine(L1Cache, "Token protocol")
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
- external_type(TBETable) {
+ structure(TBETable, external="yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
bool isPresent(Address);
}
- external_type(PersistentTable) {
+ structure(PersistentTable, external="yes") {
void persistentRequestLock(Address, MachineID, AccessType);
void persistentRequestUnlock(Address, MachineID);
bool okToIssueStarving(Address, MachineID);
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
index e685984c5..6f43e7712 100644
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -127,14 +127,14 @@ machine(L2Cache, "Token protocol")
bool exclusive, default="false", desc="if local exclusive is likely";
}
- external_type(PerfectCacheMemory) {
+ structure(PerfectCacheMemory, external="yes") {
void allocate(Address);
void deallocate(Address);
DirEntry lookup(Address);
bool isTagPresent(Address);
}
- external_type(PersistentTable) {
+ structure(PersistentTable, external="yes") {
void persistentRequestLock(Address, MachineID, AccessType);
void persistentRequestUnlock(Address, MachineID);
MachineID findSmallest(Address);
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
index 14a2f0fb2..5cad4d448 100644
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -122,7 +122,7 @@ machine(Directory, "Token protocol")
Set Sharers, desc="Probable sharers of the line. More accurately, the set of processors who need to see a GetX";
}
- external_type(PersistentTable) {
+ structure(PersistentTable, external="yes") {
void persistentRequestLock(Address, MachineID, AccessType);
void persistentRequestUnlock(Address, MachineID);
bool okToIssueStarving(Address, MachineID);
@@ -145,7 +145,7 @@ machine(Directory, "Token protocol")
bool WentPersistent, desc="Did the DMA request require a persistent request";
}
- external_type(TBETable) {
+ structure(TBETable, external="yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
index e80f91995..9a090145c 100644
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -48,7 +48,7 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- external_type(DMASequencer) {
+ structure(DMASequencer, external="yes") {
void ackCallback();
void dataCallback(DataBlock);
}
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index 4bbf3bde1..4ac59940b 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -145,7 +145,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
Time FirstResponseTime, default="0", desc="the time the first response was received";
}
- external_type(TBETable) {
+ structure(TBETable, external="yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 439723d68..4946ba0f3 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -162,7 +162,7 @@ machine(Directory, "AMD Hammer-like protocol")
bool Owned, default="false", desc="Indicates whether a cache has indicated it is currently a sharer";
}
- external_type(TBETable) {
+ structure(TBETable, external="yes") {
TBE lookup(Address);
void allocate(Address);
void deallocate(Address);
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index c02af62ef..e3eb8ebeb 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -39,7 +39,7 @@ external_type(std::string, primitive="yes");
external_type(uint64, primitive="yes");
external_type(Time, primitive="yes", default="0");
external_type(Address);
-external_type(DataBlock, desc="..."){
+structure(DataBlock, external = "yes", desc="..."){
void clear();
void copyPartial(DataBlock, int, int);
}
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index f8783230e..c856dd921 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -40,7 +40,7 @@ external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes");
external_type(OutPort, primitive="yes");
-external_type(InPort, primitive="yes") {
+structure(InPort, external = "yes", primitive="yes") {
bool isReady();
void dequeue();
int dequeue_getDelayCycles();
@@ -53,7 +53,7 @@ external_type(MachineID);
MessageBuffer getMandatoryQueue(int core_id);
-external_type(Set, non_obj="yes") {
+structure (Set, external = "yes", non_obj="yes") {
void setSize(int);
void add(NodeID);
void addSet(Set);
@@ -70,7 +70,7 @@ external_type(Set, non_obj="yes") {
NodeID smallestElement();
}
-external_type(NetDest, non_obj="yes") {
+structure (NetDest, external = "yes", non_obj="yes") {
void setSize(int);
void setSize(int, int);
void add(NodeID);
@@ -98,7 +98,7 @@ external_type(NetDest, non_obj="yes") {
MachineID smallestElement(MachineType);
}
-external_type(Sequencer) {
+structure (Sequencer, external = "yes") {
void readCallback(Address, DataBlock);
void readCallback(Address, GenericMachineType, DataBlock);
void readCallback(Address, GenericMachineType, DataBlock, Time, Time, Time);
@@ -111,7 +111,7 @@ external_type(Sequencer) {
external_type(AbstractEntry, primitive="yes");
-external_type(DirectoryMemory) {
+structure (DirectoryMemory, external = "yes") {
AbstractEntry lookup(Address);
bool isPresent(Address);
void invalidateBlock(Address);
@@ -119,7 +119,7 @@ external_type(DirectoryMemory) {
external_type(AbstractCacheEntry, primitive="yes");
-external_type(CacheMemory) {
+structure (CacheMemory, external = "yes") {
bool cacheAvail(Address);
Address cacheProbe(Address);
AbstractCacheEntry allocate(Address, AbstractCacheEntry);
@@ -135,16 +135,16 @@ external_type(CacheMemory) {
void setMRU(Address);
}
-external_type(MemoryControl, inport="yes", outport="yes") {
+structure (MemoryControl, inport="yes", outport="yes", external = "yes") {
}
-external_type(DMASequencer) {
+structure (DMASequencer, external = "yes") {
void ackCallback();
void dataCallback(DataBlock);
}
-external_type(TimerTable, inport="yes") {
+structure (TimerTable, inport="yes", external = "yes") {
bool isReady();
Address readyAddress();
void set(Address, int);
@@ -152,8 +152,7 @@ external_type(TimerTable, inport="yes") {
bool isSet(Address);
}
-external_type(GenericBloomFilter) {
-
+structure (GenericBloomFilter, external = "yes") {
void clear(int);
void increment(Address, int);
void decrement(Address, int);
@@ -163,7 +162,3 @@ external_type(GenericBloomFilter) {
bool isSet(Address, int);
int getCount(Address, int);
}
-
-
-
-
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 05:41:53 +0000