diff options
Diffstat (limited to 'src/mem/protocol')
21 files changed, 287 insertions, 299 deletions
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm index 85c9be19b..fd1b85e0d 100644 --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm @@ -350,7 +350,7 @@ machine(L0Cache, "MESI Directory L0 Cache") // ACTIONS action(a_issueGETS, "a", desc="Issue GETS") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestNetwork_out, CoherenceMsg, latency=request_latency) { + enqueue(requestNetwork_out, CoherenceMsg, request_latency) { out_msg.Addr := address; out_msg.Class := CoherenceClass:GETS; out_msg.Sender := machineID; @@ -365,7 +365,7 @@ machine(L0Cache, "MESI Directory L0 Cache") action(b_issueGETX, "b", desc="Issue GETX") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestNetwork_out, CoherenceMsg, latency=request_latency) { + enqueue(requestNetwork_out, CoherenceMsg, request_latency) { out_msg.Addr := address; out_msg.Class := CoherenceClass:GETX; out_msg.Sender := machineID; @@ -382,7 +382,7 @@ machine(L0Cache, "MESI Directory L0 Cache") action(c_issueUPGRADE, "c", desc="Issue GETX") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestNetwork_out, CoherenceMsg, latency= request_latency) { + enqueue(requestNetwork_out, CoherenceMsg, request_latency) { out_msg.Addr := address; out_msg.Class := CoherenceClass:UPGRADE; out_msg.Sender := machineID; @@ -397,7 +397,7 @@ machine(L0Cache, "MESI Directory L0 Cache") } action(f_sendDataToL1, "f", desc="send data to the L2 cache") { - enqueue(requestNetwork_out, CoherenceMsg, latency=response_latency) { + enqueue(requestNetwork_out, CoherenceMsg, response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Class := CoherenceClass:INV_DATA; @@ -411,7 +411,7 @@ machine(L0Cache, "MESI Directory L0 Cache") action(fi_sendInvAck, "fi", desc="send data to the L2 cache") { peek(messgeBuffer_in, CoherenceMsg) { - enqueue(requestNetwork_out, CoherenceMsg, latency=response_latency) { + enqueue(requestNetwork_out, CoherenceMsg, response_latency) { out_msg.Addr := address; out_msg.Class := CoherenceClass:INV_ACK; out_msg.Sender := machineID; @@ -429,7 +429,7 @@ machine(L0Cache, "MESI Directory L0 Cache") } action(g_issuePUTX, "g", desc="send data to the L2 cache") { - enqueue(requestNetwork_out, CoherenceMsg, latency=response_latency) { + enqueue(requestNetwork_out, CoherenceMsg, response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Class := CoherenceClass:PUTX; diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm index 2b6d0662f..43a9a49cf 100644 --- a/src/mem/protocol/MESI_Three_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm @@ -370,7 +370,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") // ACTIONS action(a_issueGETS, "a", desc="Issue GETS") { peek(messageBufferFromL0_in, CoherenceMsg) { - enqueue(requestNetwork_out, RequestMsg, latency=l1_request_latency) { + enqueue(requestNetwork_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; @@ -386,7 +386,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(b_issueGETX, "b", desc="Issue GETX") { peek(messageBufferFromL0_in, CoherenceMsg) { - enqueue(requestNetwork_out, RequestMsg, latency=l1_request_latency) { + enqueue(requestNetwork_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; @@ -403,7 +403,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(c_issueUPGRADE, "c", desc="Issue GETX") { peek(messageBufferFromL0_in, CoherenceMsg) { - enqueue(requestNetwork_out, RequestMsg, latency= l1_request_latency) { + enqueue(requestNetwork_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:UPGRADE; out_msg.Requestor := machineID; @@ -419,7 +419,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(d_sendDataToRequestor, "d", desc="send data to requestor") { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -433,7 +433,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") { - enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -448,7 +448,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -462,7 +462,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") { - enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -477,7 +477,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -488,7 +488,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(f_sendDataToL2, "f", desc="send data to the L2 cache") { - enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -502,7 +502,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") { - enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -517,7 +517,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(fi_sendInvAck, "fi", desc="send data to the L2 cache") { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -529,7 +529,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(forward_eviction_to_L0, "\cc", desc="sends eviction information to the processor") { - enqueue(bufferToL0_out, CoherenceMsg, latency=l1_request_latency) { + enqueue(bufferToL0_out, CoherenceMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Class := CoherenceClass:INV; out_msg.Sender := machineID; @@ -539,7 +539,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(g_issuePUTX, "g", desc="send data to the L2 cache") { - enqueue(requestNetwork_out, RequestMsg, latency=l1_response_latency) { + enqueue(requestNetwork_out, RequestMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTX; @@ -557,7 +557,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(j_sendUnblock, "j", desc="send unblock to the L2 cache") { - enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) { + enqueue(unblockNetwork_out, ResponseMsg, to_l2_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; @@ -569,7 +569,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") { - enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) { + enqueue(unblockNetwork_out, ResponseMsg, to_l2_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK; out_msg.Sender := machineID; @@ -582,7 +582,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(h_data_to_l0, "h", desc="If not prefetch, send data to the L0 cache.") { - enqueue(bufferToL0_out, CoherenceMsg, latency=l1_response_latency) { + enqueue(bufferToL0_out, CoherenceMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; @@ -596,7 +596,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(h_stale_data_to_l0, "hs", desc="If not prefetch, send data to the L0 cache.") { - enqueue(bufferToL0_out, CoherenceMsg, latency=l1_response_latency) { + enqueue(bufferToL0_out, CoherenceMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; @@ -610,7 +610,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(hh_xdata_to_l0, "\h", desc="If not prefetch, notify sequencer that store completed.") { - enqueue(bufferToL0_out, CoherenceMsg, latency=l1_response_latency) { + enqueue(bufferToL0_out, CoherenceMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index 49fd31207..5ccd453bf 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -485,7 +485,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } void enqueuePrefetch(Address address, RubyRequestType type) { - enqueue(optionalQueue_out, RubyRequest, latency=1) { + enqueue(optionalQueue_out, RubyRequest, 1) { out_msg.LineAddress := address; out_msg.Type := type; out_msg.AccessMode := RubyAccessMode:Supervisor; @@ -495,7 +495,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") // ACTIONS action(a_issueGETS, "a", desc="Issue GETS") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; @@ -512,8 +512,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(pa_issuePfGETS, "pa", desc="Issue prefetch GETS") { peek(optionalQueue_in, RubyRequest) { - enqueue(requestL1Network_out, RequestMsg, - latency=l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; @@ -530,7 +529,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GET_INSTR; out_msg.Requestor := machineID; @@ -548,8 +547,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(pai_issuePfGETINSTR, "pai", desc="Issue GETINSTR for prefetch request") { peek(optionalQueue_in, RubyRequest) { - enqueue(requestL1Network_out, RequestMsg, - latency=l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GET_INSTR; out_msg.Requestor := machineID; @@ -568,7 +566,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(b_issueGETX, "b", desc="Issue GETX") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; @@ -586,8 +584,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(pb_issuePfGETX, "pb", desc="Issue prefetch GETX") { peek(optionalQueue_in, RubyRequest) { - enqueue(requestL1Network_out, RequestMsg, - latency=l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; @@ -607,7 +604,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(c_issueUPGRADE, "c", desc="Issue GETX") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestL1Network_out, RequestMsg, latency= l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:UPGRADE; out_msg.Requestor := machineID; @@ -624,7 +621,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(d_sendDataToRequestor, "d", desc="send data to requestor") { peek(requestL1Network_in, RequestMsg) { - enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -638,7 +635,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") { - enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -653,7 +650,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") { peek(requestL1Network_in, RequestMsg) { - enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, l1_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -667,7 +664,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") { - enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, l1_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -682,7 +679,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") { peek(requestL1Network_in, RequestMsg) { - enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -693,7 +690,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(f_sendDataToL2, "f", desc="send data to the L2 cache") { - enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -707,7 +704,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") { - enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, l1_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -722,7 +719,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(fi_sendInvAck, "fi", desc="send data to the L2 cache") { peek(requestL1Network_in, RequestMsg) { - enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -741,7 +738,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(g_issuePUTX, "g", desc="send data to the L2 cache") { - enqueue(requestL1Network_out, RequestMsg, latency=l1_response_latency) { + enqueue(requestL1Network_out, RequestMsg, l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTX; @@ -759,7 +756,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(j_sendUnblock, "j", desc="send unblock to the L2 cache") { - enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) { + enqueue(unblockNetwork_out, ResponseMsg, to_l2_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; @@ -771,7 +768,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") { - enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) { + enqueue(unblockNetwork_out, ResponseMsg, to_l2_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK; out_msg.Sender := machineID; diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm index 5c240035a..7cd5560fc 100644 --- a/src/mem/protocol/MESI_Two_Level-L2cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm @@ -378,7 +378,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(a_issueFetchToMemory, "a", desc="fetch data from memory") { peek(L1RequestL2Network_in, RequestMsg) { - enqueue(DirRequestL2Network_out, RequestMsg, latency=l2_request_latency) { + enqueue(DirRequestL2Network_out, RequestMsg, l2_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; @@ -390,7 +390,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") { peek(L1RequestL2Network_in, RequestMsg) { - enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) { + enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := in_msg.Type; @@ -402,7 +402,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(c_exclusiveReplacement, "c", desc="Send data to memory") { - enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:MEMORY_DATA; @@ -415,7 +415,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") { - enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -425,7 +425,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") { - enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:MEMORY_DATA; @@ -439,7 +439,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") { peek(L1RequestL2Network_in, RequestMsg) { - enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -458,7 +458,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") { peek(L1RequestL2Network_in, RequestMsg) { - enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; @@ -477,7 +477,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") { peek(L1RequestL2Network_in, RequestMsg) { - enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -493,7 +493,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") { assert(is_valid(tbe)); assert(tbe.L1_GetS_IDs.count() > 0); - enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) { + enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -507,7 +507,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") { assert(is_valid(tbe)); assert(tbe.L1_GetS_IDs.count() == 1); - enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) { + enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; @@ -519,7 +519,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") { - enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) { + enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) { assert(is_valid(tbe)); assert(is_valid(cache_entry)); out_msg.Addr := address; @@ -535,7 +535,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") { - enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) { + enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; @@ -547,7 +547,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") { peek(L1RequestL2Network_in, RequestMsg) { - enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) { + enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; @@ -560,7 +560,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") { peek(L1RequestL2Network_in, RequestMsg) { - enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) { + enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; @@ -670,7 +670,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(t_sendWBAck, "t", desc="Send writeback ACK") { peek(L1RequestL2Network_in, RequestMsg) { - enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) { + enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:WB_ACK; out_msg.Sender := machineID; @@ -682,7 +682,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") { peek(L1RequestL2Network_in, RequestMsg) { - enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) { + enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm index 9e503309e..bfd4fc475 100644 --- a/src/mem/protocol/MESI_Two_Level-dir.sm +++ b/src/mem/protocol/MESI_Two_Level-dir.sm @@ -240,7 +240,7 @@ machine(Directory, "MESI Two Level directory protocol") // Actions action(a_sendAck, "a", desc="Send ack to L2") { peek(responseNetwork_in, ResponseMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:MEMORY_ACK; out_msg.Sender := machineID; @@ -252,7 +252,7 @@ machine(Directory, "MESI Two Level directory protocol") action(d_sendData, "d", desc="Send data to requestor") { peek(memQueue_in, MemoryMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:MEMORY_DATA; out_msg.Sender := machineID; @@ -270,7 +270,7 @@ machine(Directory, "MESI Two Level directory protocol") // Actions action(aa_sendAck, "aa", desc="Send ack to L2") { peek(memQueue_in, MemoryMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:MEMORY_ACK; out_msg.Sender := machineID; @@ -298,7 +298,7 @@ machine(Directory, "MESI Two Level directory protocol") action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") { peek(requestNetwork_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { + enqueue(memQueue_out, MemoryMsg, to_mem_ctrl_latency) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -314,7 +314,7 @@ machine(Directory, "MESI Two Level directory protocol") action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") { peek(responseNetwork_in, ResponseMsg) { - enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { + enqueue(memQueue_out, MemoryMsg, to_mem_ctrl_latency) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.Sender := machineID; @@ -338,7 +338,7 @@ machine(Directory, "MESI Two Level directory protocol") //added by SS for dma action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") { peek(requestNetwork_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { + enqueue(memQueue_out, MemoryMsg, to_mem_ctrl_latency) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -356,7 +356,7 @@ machine(Directory, "MESI Two Level directory protocol") action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") { peek(memQueue_in, MemoryMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be @@ -374,7 +374,7 @@ machine(Directory, "MESI Two Level directory protocol") action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") { peek(requestNetwork_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { + enqueue(memQueue_out, MemoryMsg, to_mem_ctrl_latency) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.OriginalRequestorMachId := machineID; @@ -391,7 +391,7 @@ machine(Directory, "MESI Two Level directory protocol") } action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") { - enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Destination.add(map_Address_to_DMA(address)); @@ -409,7 +409,7 @@ machine(Directory, "MESI Two Level directory protocol") action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) { + enqueue(responseNetwork_out, ResponseMsg, directory_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:INV; out_msg.Sender := machineID; @@ -422,7 +422,7 @@ machine(Directory, "MESI Two Level directory protocol") action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") { peek(responseNetwork_in, ResponseMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be @@ -453,7 +453,7 @@ machine(Directory, "MESI Two Level directory protocol") action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") { peek(responseNetwork_in, ResponseMsg) { - enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { + enqueue(memQueue_out, MemoryMsg, to_mem_ctrl_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm index 37c5f982e..b9bb68cbd 100644 --- a/src/mem/protocol/MESI_Two_Level-dma.sm +++ b/src/mem/protocol/MESI_Two_Level-dma.sm @@ -106,7 +106,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, RequestMsg, request_latency) { out_msg.Addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; @@ -119,7 +119,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, RequestMsg, request_latency) { out_msg.Addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 8aed261fa..29cf8d482 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -249,7 +249,7 @@ machine(L1Cache, "MI Example L1 Cache") // ACTIONS action(a_issueRequest, "a", desc="Issue a request") { - enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(requestNetwork_out, RequestMsg, issue_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; @@ -259,7 +259,7 @@ machine(L1Cache, "MI Example L1 Cache") } action(b_issuePUT, "b", desc="Issue a PUT request") { - enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(requestNetwork_out, RequestMsg, issue_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTX; @@ -272,7 +272,7 @@ machine(L1Cache, "MI Example L1 Cache") action(e_sendData, "e", desc="Send data from cache to requestor") { peek(forwardRequestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -286,7 +286,7 @@ machine(L1Cache, "MI Example L1 Cache") action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") { peek(forwardRequestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm index 389bc64b5..87ed57919 100644 --- a/src/mem/protocol/MI_example-dir.sm +++ b/src/mem/protocol/MI_example-dir.sm @@ -248,7 +248,7 @@ machine(Directory, "Directory protocol") action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { + enqueue(forwardNetwork_out, RequestMsg, directory_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:WB_ACK; out_msg.Requestor := in_msg.Requestor; @@ -260,7 +260,7 @@ machine(Directory, "Directory protocol") action(l_sendWriteBackAck, "la", desc="Send writeback ack to requestor") { peek(memQueue_in, MemoryMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="1") { + enqueue(forwardNetwork_out, RequestMsg, 1) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:WB_ACK; out_msg.Requestor := in_msg.OriginalRequestorMachId; @@ -272,7 +272,7 @@ machine(Directory, "Directory protocol") action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { + enqueue(forwardNetwork_out, RequestMsg, directory_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:WB_NACK; out_msg.Requestor := in_msg.Requestor; @@ -288,7 +288,7 @@ machine(Directory, "Directory protocol") action(d_sendData, "d", desc="Send data to requestor") { peek(memQueue_in, MemoryMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -301,7 +301,7 @@ machine(Directory, "Directory protocol") action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") { peek(memQueue_in, MemoryMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) { assert(is_valid(tbe)); out_msg.PhysicalAddress := address; out_msg.LineAddress := address; @@ -317,7 +317,7 @@ machine(Directory, "Directory protocol") action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") { peek(requestQueue_in, RequestMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) { assert(is_valid(tbe)); out_msg.PhysicalAddress := address; out_msg.LineAddress := address; @@ -330,7 +330,7 @@ machine(Directory, "Directory protocol") } action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) { assert(is_valid(tbe)); out_msg.PhysicalAddress := address; out_msg.LineAddress := address; @@ -353,7 +353,7 @@ machine(Directory, "Directory protocol") APPEND_TRANSITION_COMMENT(getDirectoryEntry(in_msg.Addr).Owner); APPEND_TRANSITION_COMMENT("Req: "); APPEND_TRANSITION_COMMENT(in_msg.Requestor); - enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { + enqueue(forwardNetwork_out, RequestMsg, directory_latency) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -365,7 +365,7 @@ machine(Directory, "Directory protocol") action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { + enqueue(forwardNetwork_out, RequestMsg, directory_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := machineID; @@ -440,7 +440,7 @@ machine(Directory, "Directory protocol") action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") { peek(requestQueue_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -454,7 +454,7 @@ machine(Directory, "Directory protocol") action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -468,7 +468,7 @@ machine(Directory, "Directory protocol") action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; //out_msg.OriginalRequestorMachId := machineID; @@ -484,7 +484,7 @@ machine(Directory, "Directory protocol") action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") { peek(requestQueue_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; @@ -504,7 +504,7 @@ machine(Directory, "Directory protocol") action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") { peek(requestQueue_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.Sender := machineID; diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm index 7bc8a5f5d..c9da54f85 100644 --- a/src/mem/protocol/MI_example-dma.sm +++ b/src/mem/protocol/MI_example-dma.sm @@ -101,7 +101,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, DMARequestMsg, request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:READ; @@ -116,7 +116,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, DMARequestMsg, request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:WRITE; diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 40ac524d6..bf935ab65 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -414,7 +414,7 @@ machine(L1Cache, "Directory protocol") action(a_issueGETS, "a", desc="Issue GETS") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestNetwork_out, RequestMsg, latency= request_latency) { + enqueue(requestNetwork_out, RequestMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; @@ -430,7 +430,7 @@ machine(L1Cache, "Directory protocol") action(b_issueGETX, "b", desc="Issue GETX") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestNetwork_out, RequestMsg, latency=request_latency) { + enqueue(requestNetwork_out, RequestMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; @@ -445,8 +445,7 @@ machine(L1Cache, "Directory protocol") } action(d_issuePUTX, "d", desc="Issue PUTX") { - // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) { - enqueue(requestNetwork_out, RequestMsg, latency=request_latency) { + enqueue(requestNetwork_out, RequestMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTX; out_msg.Requestor := machineID; @@ -458,8 +457,7 @@ machine(L1Cache, "Directory protocol") } action(dd_issuePUTO, "\d", desc="Issue PUTO") { - // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) { - enqueue(requestNetwork_out, RequestMsg, latency=request_latency) { + enqueue(requestNetwork_out, RequestMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTO; out_msg.Requestor := machineID; @@ -471,8 +469,7 @@ machine(L1Cache, "Directory protocol") } action(dd_issuePUTS, "\ds", desc="Issue PUTS") { - // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) { - enqueue(requestNetwork_out, RequestMsg, latency=request_latency) { + enqueue(requestNetwork_out, RequestMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTS; out_msg.Requestor := machineID; @@ -487,7 +484,7 @@ machine(L1Cache, "Directory protocol") peek(requestNetwork_in, RequestMsg) { assert(is_valid(cache_entry)); if (in_msg.RequestorMachine == MachineType:L2Cache) { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -503,7 +500,7 @@ machine(L1Cache, "Directory protocol") DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.Addr); } else { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -521,7 +518,7 @@ machine(L1Cache, "Directory protocol") } action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -540,7 +537,7 @@ machine(L1Cache, "Directory protocol") peek(requestNetwork_in, RequestMsg) { assert(is_valid(cache_entry)); if (in_msg.RequestorMachine == MachineType:L2Cache) { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -555,7 +552,7 @@ machine(L1Cache, "Directory protocol") DPRINTF(RubySlicc, "Sending exclusive data to L2\n"); } else { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -574,7 +571,7 @@ machine(L1Cache, "Directory protocol") action(f_sendAck, "f", desc="Send ack from cache to requestor") { peek(requestNetwork_in, RequestMsg) { if (in_msg.RequestorMachine == MachineType:L1Cache) { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -585,7 +582,7 @@ machine(L1Cache, "Directory protocol") } } else { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -600,7 +597,7 @@ machine(L1Cache, "Directory protocol") } action(g_sendUnblock, "g", desc="Send unblock to memory") { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; @@ -612,7 +609,7 @@ machine(L1Cache, "Directory protocol") } action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to memory") { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE; out_msg.Sender := machineID; @@ -709,7 +706,7 @@ machine(L1Cache, "Directory protocol") action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DMA_ACK; out_msg.Sender := machineID; @@ -728,7 +725,7 @@ machine(L1Cache, "Directory protocol") assert(is_valid(tbe)); if (in_msg.RequestorMachine == MachineType:L1Cache || in_msg.RequestorMachine == MachineType:DMA) { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -742,7 +739,7 @@ machine(L1Cache, "Directory protocol") } } else { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -763,7 +760,7 @@ machine(L1Cache, "Directory protocol") peek(requestNetwork_in, RequestMsg) { assert(is_valid(tbe)); if (in_msg.RequestorMachine == MachineType:L1Cache) { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -776,7 +773,7 @@ machine(L1Cache, "Directory protocol") } } else { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -794,7 +791,7 @@ machine(L1Cache, "Directory protocol") // L2 will usually request data for a writeback action(qq_sendWBDataFromTBEToL2, "\q", desc="Send data from TBE to L2") { - enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { + enqueue(responseNetwork_out, ResponseMsg, request_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Sender := machineID; diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm index 628dfa7a0..5974321b7 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -683,7 +683,7 @@ machine(L2Cache, "Token protocol") action(a_issueGETS, "a", desc="issue local request globally") { peek(L1requestNetwork_in, RequestMsg) { - enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) { + enqueue(globalRequestNetwork_out, RequestMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.RequestorMachine := MachineType:L2Cache; @@ -696,7 +696,7 @@ machine(L2Cache, "Token protocol") action(a_issueGETX, "\a", desc="issue local request globally") { peek(L1requestNetwork_in, RequestMsg) { - enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) { + enqueue(globalRequestNetwork_out, RequestMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.RequestorMachine := MachineType:L2Cache; @@ -708,7 +708,7 @@ machine(L2Cache, "Token protocol") } action(b_issuePUTX, "b", desc="Issue PUTX") { - enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) { + enqueue(globalRequestNetwork_out, RequestMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTX; out_msg.RequestorMachine := MachineType:L2Cache; @@ -719,7 +719,7 @@ machine(L2Cache, "Token protocol") } action(b_issuePUTO, "\b", desc="Issue PUTO") { - enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) { + enqueue(globalRequestNetwork_out, RequestMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTO; out_msg.Requestor := machineID; @@ -731,7 +731,7 @@ machine(L2Cache, "Token protocol") /* PUTO, but local sharers exist */ action(b_issuePUTO_ls, "\bb", desc="Issue PUTO") { - enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) { + enqueue(globalRequestNetwork_out, RequestMsg, request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTO_SHARERS; out_msg.Requestor := machineID; @@ -743,7 +743,7 @@ machine(L2Cache, "Token protocol") action(c_sendDataFromTBEToL1GETS, "c", desc="Send data from TBE to L1 requestors in TBE") { assert(is_valid(tbe)); - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -761,7 +761,7 @@ machine(L2Cache, "Token protocol") action(c_sendDataFromTBEToL1GETX, "\c", desc="Send data from TBE to L1 requestors in TBE") { assert(is_valid(tbe)); - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -778,7 +778,7 @@ machine(L2Cache, "Token protocol") action(c_sendExclusiveDataFromTBEToL1GETS, "\cc", desc="Send data from TBE to L1 requestors in TBE") { assert(is_valid(tbe)); - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -792,7 +792,7 @@ machine(L2Cache, "Token protocol") action(c_sendDataFromTBEToFwdGETX, "cc", desc="Send data from TBE to external GETX") { assert(is_valid(tbe)); - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -808,7 +808,7 @@ machine(L2Cache, "Token protocol") action(cd_sendDataFromTBEToFwdDma, "cd", desc="Send data from TBE to external GETX") { assert(is_valid(tbe)); peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -828,7 +828,7 @@ machine(L2Cache, "Token protocol") action(c_sendDataFromTBEToFwdGETS, "ccc", desc="Send data from TBE to external GETX") { assert(is_valid(tbe)); - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -847,7 +847,7 @@ machine(L2Cache, "Token protocol") action(c_sendExclusiveDataFromTBEToFwdGETS, "\ccc", desc="Send data from TBE to external GETX") { assert(is_valid(tbe)); - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -865,7 +865,7 @@ machine(L2Cache, "Token protocol") action(d_sendDataToL1GETS, "d", desc="Send data directly to L1 requestor") { assert(is_valid(cache_entry)); peek(L1requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -885,7 +885,7 @@ machine(L2Cache, "Token protocol") action(d_sendDataToL1GETX, "\d", desc="Send data and a token from TBE to L1 requestor") { assert(is_valid(cache_entry)); peek(L1requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; @@ -905,7 +905,7 @@ machine(L2Cache, "Token protocol") action(dd_sendDataToFwdGETX, "dd", desc="send data") { assert(is_valid(cache_entry)); peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -925,7 +925,7 @@ machine(L2Cache, "Token protocol") action(dd_sendDataToFwdGETS, "\dd", desc="send data") { assert(is_valid(cache_entry)); peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -945,7 +945,7 @@ machine(L2Cache, "Token protocol") action(dd_sendExclusiveDataToFwdGETS, "\d\d", desc="send data") { assert(is_valid(cache_entry)); peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -959,7 +959,7 @@ machine(L2Cache, "Token protocol") } action(e_sendAck, "e", desc="Send ack with the tokens we've collected thus far.") { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; @@ -974,7 +974,7 @@ machine(L2Cache, "Token protocol") action(e_sendAckToL1Requestor, "\e", desc="Send ack with the tokens we've collected thus far.") { peek(L1requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -987,7 +987,7 @@ machine(L2Cache, "Token protocol") } action(e_sendAckToL1RequestorFromTBE, "eee", desc="Send ack with the tokens we've collected thus far.") { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; @@ -1010,7 +1010,7 @@ machine(L2Cache, "Token protocol") DPRINTF(RubySlicc, "%s\n", getLocalOwner(cache_entry, address)); } - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := machineID; @@ -1031,7 +1031,7 @@ machine(L2Cache, "Token protocol") tbe.NumIntPendingAcks := countLocalSharers(cache_entry, address); if (countLocalSharers(cache_entry, address) > 0) { - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := machineID; @@ -1063,7 +1063,7 @@ machine(L2Cache, "Token protocol") tbe.NumIntPendingAcks := countLocalSharers(cache_entry, address); } - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := in_msg.Requestor; @@ -1089,7 +1089,7 @@ machine(L2Cache, "Token protocol") tbe.NumIntPendingAcks := countLocalSharers(cache_entry, address); } } - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := tbe.L1_GetX_ID; @@ -1102,7 +1102,7 @@ machine(L2Cache, "Token protocol") action(f_sendUnblock, "f", desc="Send unblock to global directory") { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -1114,7 +1114,7 @@ machine(L2Cache, "Token protocol") action(f_sendExclusiveUnblock, "\f", desc="Send unblock to global directory") { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -1197,7 +1197,7 @@ machine(L2Cache, "Token protocol") action(j_forwardGlobalRequestToLocalOwner, "j", desc="Forward external request to local owner") { peek(requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := in_msg.Addr; out_msg.Type := in_msg.Type; out_msg.Requestor := machineID; @@ -1212,7 +1212,7 @@ machine(L2Cache, "Token protocol") action(jd_forwardDmaRequestToLocalOwner, "jd", desc="Forward dma request to local owner") { peek(requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := in_msg.Addr; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -1228,7 +1228,7 @@ machine(L2Cache, "Token protocol") action(k_forwardLocalGETSToLocalSharer, "k", desc="Forward local request to local sharer/owner") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := in_msg.Addr; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := in_msg.Requestor; @@ -1241,7 +1241,7 @@ machine(L2Cache, "Token protocol") } action(k_forwardLocalGETXToLocalOwner, "\k", desc="Forward local request to local owner") { - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; @@ -1256,7 +1256,7 @@ machine(L2Cache, "Token protocol") // same as previous except that it assumes to TBE is present to get number of acks action(kk_forwardLocalGETXToLocalExclusive, "kk", desc="Forward local request to local owner") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := in_msg.Addr; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := in_msg.Requestor; @@ -1270,7 +1270,7 @@ machine(L2Cache, "Token protocol") action(kk_forwardLocalGETSToLocalOwner, "\kk", desc="Forward local request to local owner") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := in_msg.Addr; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := in_msg.Requestor; @@ -1284,7 +1284,7 @@ machine(L2Cache, "Token protocol") action(l_writebackAckNeedData, "l", desc="Send writeback ack to L1 requesting data") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := in_msg.Addr; // out_msg.Type := CoherenceResponseType:WRITEBACK_SEND_DATA; out_msg.Type := CoherenceRequestType:WB_ACK_DATA; @@ -1298,7 +1298,7 @@ machine(L2Cache, "Token protocol") action(l_writebackAckDropData, "\l", desc="Send writeback ack to L1 indicating to drop data") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := in_msg.Addr; // out_msg.Type := CoherenceResponseType:WRITEBACK_ACK; out_msg.Type := CoherenceRequestType:WB_ACK; @@ -1312,7 +1312,7 @@ machine(L2Cache, "Token protocol") action(ll_writebackNack, "\ll", desc="Send writeback nack to L1") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { + enqueue( localRequestNetwork_out, RequestMsg, response_latency ) { out_msg.Addr := in_msg.Addr; out_msg.Type := CoherenceRequestType:WB_NACK; out_msg.Requestor := machineID; @@ -1383,7 +1383,7 @@ machine(L2Cache, "Token protocol") action( qq_sendDataFromTBEToMemory, "qq", desc="Send data from TBE to directory") { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Sender := machineID; @@ -1514,7 +1514,7 @@ machine(L2Cache, "Token protocol") } action(da_sendDmaAckUnblock, "da", desc="Send dma ack to global directory") { - enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DMA_ACK; out_msg.Destination.add(map_Address_to_Directory(address)); diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm index a8acaba02..336bb80ee 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -299,7 +299,7 @@ machine(Directory, "Directory protocol") action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { + enqueue(forwardNetwork_out, RequestMsg, directory_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:WB_ACK; out_msg.Requestor := in_msg.Requestor; @@ -312,7 +312,7 @@ machine(Directory, "Directory protocol") action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { + enqueue(forwardNetwork_out, RequestMsg, directory_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:WB_NACK; out_msg.Requestor := in_msg.Requestor; @@ -338,7 +338,7 @@ machine(Directory, "Directory protocol") action(d_sendDataMsg, "d", desc="Send data to requestor") { peek(memQueue_in, MemoryMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:Directory; @@ -359,7 +359,7 @@ machine(Directory, "Directory protocol") action(p_fwdDataToDMA, "\d", desc="Send data to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:Directory; @@ -383,7 +383,7 @@ machine(Directory, "Directory protocol") action(f_forwardRequest, "f", desc="Forward request to owner") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { + enqueue(forwardNetwork_out, RequestMsg, directory_latency) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -400,7 +400,7 @@ machine(Directory, "Directory protocol") action(f_forwardRequestDirIsRequestor, "\f", desc="Forward request to owner") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { + enqueue(forwardNetwork_out, RequestMsg, directory_latency) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Requestor := machineID; @@ -420,7 +420,7 @@ machine(Directory, "Directory protocol") if ((getDirectoryEntry(in_msg.Addr).Sharers.count() > 1) || ((getDirectoryEntry(in_msg.Addr).Sharers.count() > 0) && (getDirectoryEntry(in_msg.Addr).Sharers.isElement(in_msg.Requestor) == false))) { - enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { + enqueue(forwardNetwork_out, RequestMsg, directory_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := in_msg.Requestor; @@ -497,7 +497,7 @@ machine(Directory, "Directory protocol") action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") { peek(requestQueue_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -519,7 +519,7 @@ machine(Directory, "Directory protocol") action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") { peek(unblockNetwork_in, ResponseMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.Sender := machineID; @@ -539,7 +539,7 @@ machine(Directory, "Directory protocol") action(qw_queueMemoryWBRequest2, "/qw", desc="Queue off-chip writeback request") { peek(requestQueue_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.Sender := machineID; @@ -561,7 +561,7 @@ machine(Directory, "Directory protocol") action(a_sendDMAAck, "\a", desc="Send DMA Ack that write completed, along with Inv Ack count") { peek(requestQueue_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:Directory; @@ -576,7 +576,7 @@ machine(Directory, "Directory protocol") action(a_sendDMAAck2, "\aa", desc="Send DMA Ack that write completed, along with Inv Ack count") { peek(unblockNetwork_in, ResponseMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:Directory; diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index f4d910795..fd1ab6f6c 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -151,7 +151,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, RequestMsg, request_latency) { out_msg.Addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; @@ -166,7 +166,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, RequestMsg, request_latency) { out_msg.Addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; @@ -201,7 +201,7 @@ machine(DMA, "DMA Controller") } action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") { - enqueue(respToDirectory_out, ResponseMsg, latency=response_latency) { + enqueue(respToDirectory_out, ResponseMsg, response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE; out_msg.Destination.add(map_Address_to_Directory(address)); diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index 463ecf65f..7400ba12e 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -733,7 +733,7 @@ machine(L1Cache, "Token protocol") if (tbe.IssueCount >= retry_threshold) { // Issue a persistent request if possible if (okToIssueStarving(address, machineID) && (starving == false)) { - enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) { + enqueue(persistentNetwork_out, PersistentMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := PersistentRequestType:GETS_PERSISTENT; out_msg.Requestor := machineID; @@ -785,7 +785,7 @@ machine(L1Cache, "Token protocol") } } else { // Make a normal request - enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) { + enqueue(requestNetwork_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; @@ -804,7 +804,7 @@ machine(L1Cache, "Token protocol") } // send to other local L1s, with local bit set - enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) { + enqueue(requestNetwork_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; @@ -852,7 +852,7 @@ machine(L1Cache, "Token protocol") if (tbe.IssueCount >= retry_threshold) { // Issue a persistent request if possible if ( okToIssueStarving(address, machineID) && (starving == false)) { - enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) { + enqueue(persistentNetwork_out, PersistentMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := PersistentRequestType:GETX_PERSISTENT; out_msg.Requestor := machineID; @@ -904,7 +904,7 @@ machine(L1Cache, "Token protocol") } else { // Make a normal request - enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) { + enqueue(requestNetwork_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; @@ -925,7 +925,7 @@ machine(L1Cache, "Token protocol") } // send to other local L1s too - enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) { + enqueue(requestNetwork_out, RequestMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; @@ -966,7 +966,7 @@ machine(L1Cache, "Token protocol") action(bb_bounceResponse, "\b", desc="Bounce tokens and data to memory") { peek(responseNetwork_in, ResponseMsg) { // FIXME, should use a 3rd vnet - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Sender := machineID; @@ -981,7 +981,7 @@ machine(L1Cache, "Token protocol") action(c_ownedReplacement, "c", desc="Issue writeback") { assert(is_valid(cache_entry)); - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Sender := machineID; @@ -1005,7 +1005,7 @@ machine(L1Cache, "Token protocol") // don't send writeback if replacing block with no tokens assert(is_valid(cache_entry)); assert (cache_entry.Tokens > 0); - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Sender := machineID; @@ -1027,7 +1027,7 @@ machine(L1Cache, "Token protocol") action(tr_tokenReplacement, "tr", desc="Issue token writeback") { assert(is_valid(cache_entry)); if (cache_entry.Tokens > 0) { - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Sender := machineID; @@ -1052,7 +1052,7 @@ machine(L1Cache, "Token protocol") action(d_sendDataWithToken, "d", desc="Send data and a token from cache to requestor") { assert(is_valid(cache_entry)); peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; @@ -1076,7 +1076,7 @@ machine(L1Cache, "Token protocol") assert(is_valid(cache_entry)); peek(requestNetwork_in, RequestMsg) { if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) { - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; @@ -1094,7 +1094,7 @@ machine(L1Cache, "Token protocol") cache_entry.Tokens := cache_entry.Tokens - N_tokens; } else if (cache_entry.Tokens > 1) { - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; @@ -1118,7 +1118,7 @@ machine(L1Cache, "Token protocol") action(dd_sendDataWithAllTokens, "\d", desc="Send data and all tokens from cache to requestor") { peek(requestNetwork_in, RequestMsg) { assert(is_valid(cache_entry)); - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -1141,7 +1141,7 @@ machine(L1Cache, "Token protocol") // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself assert(is_valid(cache_entry)); if (cache_entry.Tokens > 0) { - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; if (cache_entry.Tokens > (max_tokens() / 2)) { out_msg.Type := CoherenceResponseType:DATA_OWNER; @@ -1163,7 +1163,7 @@ machine(L1Cache, "Token protocol") //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself assert(is_valid(cache_entry)); assert(cache_entry.Tokens > 0); - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -1182,7 +1182,7 @@ machine(L1Cache, "Token protocol") assert(is_valid(cache_entry)); assert(cache_entry.Tokens > 0); if (cache_entry.Tokens > 1) { - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; if (cache_entry.Tokens > (max_tokens() / 2)) { out_msg.Type := CoherenceResponseType:DATA_OWNER; @@ -1212,7 +1212,7 @@ machine(L1Cache, "Token protocol") //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself assert(is_valid(cache_entry)); assert(cache_entry.Tokens > ((max_tokens() / 2) + 1)); - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -1237,7 +1237,7 @@ machine(L1Cache, "Token protocol") action(fo_sendDataWithOwnerToken, "fo", desc="Send data and owner tokens") { assert(is_valid(cache_entry)); assert(cache_entry.Tokens == ((max_tokens() / 2) + 1)); - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -1257,7 +1257,7 @@ machine(L1Cache, "Token protocol") peek(responseNetwork_in, ResponseMsg) { // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself // FIXME, should use a 3rd vnet in some cases - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Sender := machineID; @@ -1369,7 +1369,7 @@ machine(L1Cache, "Token protocol") } action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all tokens") { - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:INV; out_msg.Tokens := 0; @@ -1403,7 +1403,7 @@ machine(L1Cache, "Token protocol") if (tbe.WentPersistent) { // assert(starving == true); outstandingRequests := outstandingRequests - 1; - enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) { + enqueue(persistentNetwork_out, PersistentMsg, l1_request_latency) { out_msg.Addr := address; out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT; out_msg.Requestor := machineID; @@ -1450,7 +1450,7 @@ machine(L1Cache, "Token protocol") assert(is_valid(cache_entry)); if (cache_entry.Tokens > 0) { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) { out_msg.Addr := address; if (cache_entry.Tokens > (max_tokens() / 2)) { out_msg.Type := CoherenceResponseType:DATA_OWNER; diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm index c7b2a618d..b429a68aa 100644 --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm @@ -482,9 +482,7 @@ machine(L2Cache, "Token protocol") peek(L1requestNetwork_in, RequestMsg) { // if this is a retry or no local sharers, broadcast normally - - // if (in_msg.RetryNum > 0 || (in_msg.Type == CoherenceRequestType:GETX && exclusiveExists(in_msg.Addr) == false) || (in_msg.Type == CoherenceRequestType:GETS && sharersExist(in_msg.Addr) == false)) { - enqueue(globalRequestNetwork_out, RequestMsg, latency=l2_request_latency) { + enqueue(globalRequestNetwork_out, RequestMsg, l2_request_latency) { out_msg.Addr := in_msg.Addr; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -513,7 +511,7 @@ machine(L2Cache, "Token protocol") action(bb_bounceResponse, "\b", desc="Bounce tokens and data to memory") { peek(responseNetwork_in, ResponseMsg) { // FIXME, should use a 3rd vnet - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Sender := machineID; @@ -529,7 +527,7 @@ machine(L2Cache, "Token protocol") action(c_cleanReplacement, "c", desc="Issue clean writeback") { assert(is_valid(cache_entry)); if (cache_entry.Tokens > 0) { - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -543,7 +541,7 @@ machine(L2Cache, "Token protocol") action(cc_dirtyReplacement, "\c", desc="Issue dirty writeback") { assert(is_valid(cache_entry)); - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Sender := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -566,7 +564,7 @@ machine(L2Cache, "Token protocol") peek(requestNetwork_in, RequestMsg) { assert(is_valid(cache_entry)); if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) { - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; @@ -579,7 +577,7 @@ machine(L2Cache, "Token protocol") cache_entry.Tokens := cache_entry.Tokens - N_tokens; } else { - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; @@ -597,7 +595,7 @@ machine(L2Cache, "Token protocol") action(dd_sendDataWithAllTokens, "\d", desc="Send data and all tokens from cache to requestor") { assert(is_valid(cache_entry)); peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -615,7 +613,7 @@ machine(L2Cache, "Token protocol") action(e_sendAckWithCollectedTokens, "e", desc="Send ack with the tokens we've collected thus far.") { assert(is_valid(cache_entry)); if (cache_entry.Tokens > 0) { - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -630,7 +628,7 @@ machine(L2Cache, "Token protocol") action(ee_sendDataWithAllTokens, "\e", desc="Send data and all tokens from cache to starver") { assert(is_valid(cache_entry)); - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -649,7 +647,7 @@ machine(L2Cache, "Token protocol") assert(is_valid(cache_entry)); assert(cache_entry.Tokens > 0); if (cache_entry.Tokens > 1) { - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -666,7 +664,7 @@ machine(L2Cache, "Token protocol") //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself assert(is_valid(cache_entry)); assert(cache_entry.Tokens > (max_tokens() / 2) + 1); - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -683,7 +681,7 @@ machine(L2Cache, "Token protocol") //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself assert(is_valid(cache_entry)); assert(cache_entry.Tokens == (max_tokens() / 2) + 1); - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -702,7 +700,7 @@ machine(L2Cache, "Token protocol") // assert(persistentTable.isLocked(address)); peek(responseNetwork_in, ResponseMsg) { // FIXME, should use a 3rd vnet in some cases - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Sender := machineID; @@ -719,7 +717,7 @@ machine(L2Cache, "Token protocol") //assert(persistentTable.isLocked(address)); peek(responseNetwork_in, ResponseMsg) { // FIXME, should use a 3rd vnet in some cases - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; if (in_msg.Type == CoherenceResponseType:WB_SHARED_DATA) { out_msg.Type := CoherenceResponseType:DATA_SHARED; @@ -741,7 +739,7 @@ machine(L2Cache, "Token protocol") // assert(persistentTable.isLocked(address)); peek(responseNetwork_in, ResponseMsg) { // FIXME, should use a 3rd vnet in some cases - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -769,7 +767,7 @@ machine(L2Cache, "Token protocol") in_msg.RetryNum); } else { - enqueue(localRequestNetwork_out, RequestMsg, latency=l2_response_latency ) { + enqueue(localRequestNetwork_out, RequestMsg, l2_response_latency ) { out_msg.Addr := in_msg.Addr; out_msg.Requestor := in_msg.Requestor; @@ -795,8 +793,7 @@ machine(L2Cache, "Token protocol") peek(L1requestNetwork_in, RequestMsg) { assert(is_valid(cache_entry)); assert(cache_entry.Tokens > 0); - //enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="L2_to_L1_RESPONSE_LATENCY") { - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; @@ -814,7 +811,7 @@ machine(L2Cache, "Token protocol") peek(L1requestNetwork_in, RequestMsg) { assert(is_valid(cache_entry)); assert(cache_entry.Tokens == (max_tokens() / 2) + 1); - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -832,8 +829,7 @@ machine(L2Cache, "Token protocol") peek(L1requestNetwork_in, RequestMsg) { assert(is_valid(cache_entry)); // assert(cache_entry.Tokens == max_tokens()); - //enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="L2_to_L1_RESPONSE_LATENCY") { - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -908,7 +904,7 @@ machine(L2Cache, "Token protocol") assert(is_valid(cache_entry)); if (cache_entry.Tokens > 0) { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -926,7 +922,7 @@ machine(L2Cache, "Token protocol") assert(is_valid(cache_entry)); if (cache_entry.Tokens > 0) { peek(L1requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm index ab2ae2365..f7d3f1fa2 100644 --- a/src/mem/protocol/MOESI_CMP_token-dir.sm +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm @@ -413,8 +413,7 @@ machine(Directory, "Token protocol") // Only send a message if we have tokens to send if (getDirectoryEntry(address).Tokens > 0) { peek(requestNetwork_in, RequestMsg) { - // enqueue(responseNetwork_out, ResponseMsg, latency="DIRECTORY_CACHE_LATENCY") {// FIXME? - enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {// FIXME? + enqueue(responseNetwork_out, ResponseMsg, directory_latency) {// FIXME? out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -429,7 +428,7 @@ machine(Directory, "Token protocol") action(px_tryIssuingPersistentGETXRequest, "px", desc="...") { if (okToIssueStarving(address, machineID) && (starving == false)) { - enqueue(persistentNetwork_out, PersistentMsg, latency = "1") { + enqueue(persistentNetwork_out, PersistentMsg, 1) { out_msg.Addr := address; out_msg.Type := PersistentRequestType:GETX_PERSISTENT; out_msg.Requestor := machineID; @@ -474,7 +473,7 @@ machine(Directory, "Token protocol") // Assser that we only send message if we don't already have all the tokens // assert(getDirectoryEntry(address).Tokens != max_tokens()); - enqueue(requestNetwork_out, RequestMsg, latency = "1") { + enqueue(requestNetwork_out, RequestMsg, 1) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; @@ -497,7 +496,7 @@ machine(Directory, "Token protocol") action(ps_tryIssuingPersistentGETSRequest, "ps", desc="...") { if (okToIssueStarving(address, machineID) && (starving == false)) { - enqueue(persistentNetwork_out, PersistentMsg, latency = "1") { + enqueue(persistentNetwork_out, PersistentMsg, 1) { out_msg.Addr := address; out_msg.Type := PersistentRequestType:GETS_PERSISTENT; out_msg.Requestor := machineID; @@ -538,7 +537,7 @@ machine(Directory, "Token protocol") action(br_broadcastRead, "br", desc="Broadcast GETS for data") { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(requestNetwork_out, RequestMsg, latency = "1") { + enqueue(requestNetwork_out, RequestMsg, 1) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; @@ -562,8 +561,7 @@ machine(Directory, "Token protocol") action(aa_sendTokensToStarver, "\a", desc="Send tokens to starver") { // Only send a message if we have tokens to send if (getDirectoryEntry(address).Tokens > 0) { - // enqueue(responseNetwork_out, ResponseMsg, latency="DIRECTORY_CACHE_LATENCY") {// FIXME? - enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {// FIXME? + enqueue(responseNetwork_out, ResponseMsg, directory_latency) {// FIXME? out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -577,7 +575,7 @@ machine(Directory, "Token protocol") action(d_sendMemoryDataWithAllTokens, "d", desc="Send data and tokens to requestor") { peek(memQueue_in, MemoryMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -594,7 +592,7 @@ machine(Directory, "Token protocol") action(dd_sendMemDataToStarver, "\d", desc="Send data and tokens to starver") { peek(memQueue_in, MemoryMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -610,7 +608,7 @@ machine(Directory, "Token protocol") } action(de_sendTbeDataToStarver, "de", desc="Send data and tokens to starver") { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -626,7 +624,7 @@ machine(Directory, "Token protocol") action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") { peek(requestNetwork_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -639,7 +637,7 @@ machine(Directory, "Token protocol") } action(qp_queueMemoryForPersistent, "qp", desc="Queue off-chip fetch request") { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -652,7 +650,7 @@ machine(Directory, "Token protocol") action(fd_memoryDma, "fd", desc="Queue off-chip fetch request") { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -665,7 +663,7 @@ machine(Directory, "Token protocol") } action(lq_queueMemoryWbRequest, "lq", desc="Write data to memory") { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.DataBlk := getDirectoryEntry(address).DataBlk; @@ -674,7 +672,7 @@ machine(Directory, "Token protocol") } action(ld_queueMemoryDmaWriteFromTbe, "ld", desc="Write DMA data to memory") { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; // first, initialize the data blk to the current version of system memory @@ -686,7 +684,7 @@ machine(Directory, "Token protocol") } action(lr_queueMemoryDmaReadWriteback, "lr", desc="Write DMA data from read to memory") { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; // first, initialize the data blk to the current version of system memory @@ -712,7 +710,7 @@ machine(Directory, "Token protocol") if (tbe.WentPersistent) { assert(starving == true); - enqueue(persistentNetwork_out, PersistentMsg, latency = "1") { + enqueue(persistentNetwork_out, PersistentMsg, 1) { out_msg.Addr := address; out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT; out_msg.Requestor := machineID; @@ -813,7 +811,7 @@ machine(Directory, "Token protocol") action(r_bounceResponse, "r", desc="Bounce response to starving processor") { peek(responseNetwork_in, ResponseMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Sender := machineID; @@ -864,7 +862,7 @@ machine(Directory, "Token protocol") // Bounce the message, but "re-associate" the data and the owner // token. In essence we're converting an ACK_OWNER message to a // DATA_OWNER message, keeping the number of tokens the same. - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_OWNER; out_msg.Sender := machineID; @@ -878,7 +876,7 @@ machine(Directory, "Token protocol") } action(da_sendDmaAck, "da", desc="Send Ack to DMA controller") { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) { out_msg.PhysicalAddress := address; out_msg.LineAddress := address; out_msg.Type := DMAResponseType:ACK; @@ -889,7 +887,7 @@ machine(Directory, "Token protocol") action(dm_sendMemoryDataToDma, "dm", desc="Send Data to DMA controller from memory") { peek(memQueue_in, MemoryMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) { out_msg.PhysicalAddress := address; out_msg.LineAddress := address; out_msg.Type := DMAResponseType:DATA; @@ -906,7 +904,7 @@ machine(Directory, "Token protocol") action(dd_sendDmaData, "dd", desc="Send Data to DMA controller") { peek(responseNetwork_in, ResponseMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) { out_msg.PhysicalAddress := address; out_msg.LineAddress := address; out_msg.Type := DMAResponseType:DATA; diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm index d09a552db..812017acd 100644 --- a/src/mem/protocol/MOESI_CMP_token-dma.sm +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm @@ -106,7 +106,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, DMARequestMsg, request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:READ; @@ -121,7 +121,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, DMARequestMsg, request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:WRITE; diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index b99a03098..514488115 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -534,7 +534,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") // ACTIONS action(a_issueGETS, "a", desc="Issue GETS") { - enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(requestNetwork_out, RequestMsg, issue_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; @@ -549,7 +549,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } action(b_issueGETX, "b", desc="Issue GETX") { - enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(requestNetwork_out, RequestMsg, issue_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; @@ -565,7 +565,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(b_issueGETXIfMoreThanOne, "bo", desc="Issue GETX") { if (machineCount(MachineType:L1Cache) > 1) { - enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(requestNetwork_out, RequestMsg, issue_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; @@ -581,7 +581,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } action(bf_issueGETF, "bf", desc="Issue GETF") { - enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(requestNetwork_out, RequestMsg, issue_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETF; @@ -597,7 +597,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(c_sendExclusiveData, "c", desc="Send exclusive data from cache to requestor") { peek(forwardToCache_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; @@ -620,7 +620,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(ct_sendExclusiveDataFromTBE, "ct", desc="Send exclusive data from tbe to requestor") { peek(forwardToCache_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; @@ -642,7 +642,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } action(d_issuePUT, "d", desc="Issue PUT") { - enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(requestNetwork_out, RequestMsg, issue_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUT; out_msg.Requestor := machineID; @@ -652,7 +652,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } action(df_issuePUTF, "df", desc="Issue PUTF") { - enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(requestNetwork_out, RequestMsg, issue_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTF; out_msg.Requestor := machineID; @@ -663,7 +663,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(e_sendData, "e", desc="Send data from cache to requestor") { peek(forwardToCache_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -686,7 +686,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(ee_sendDataShared, "\e", desc="Send data from cache to requestor, remaining the owner") { peek(forwardToCache_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; @@ -710,7 +710,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(et_sendDataSharedFromTBE, "\et", desc="Send data from TBE to requestor, keep a shared copy") { peek(forwardToCache_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; @@ -734,7 +734,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(em_sendDataSharedMultiple, "em", desc="Send data from cache to all requestors, still the owner") { peek(forwardToCache_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; @@ -754,7 +754,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(emt_sendDataSharedMultipleFromTBE, "emt", desc="Send data from tbe to all requestors") { peek(forwardToCache_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; @@ -774,7 +774,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(f_sendAck, "f", desc="Send ack from cache to requestor") { peek(forwardToCache_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -791,7 +791,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(ff_sendAckShared, "\f", desc="Send shared ack from cache to requestor") { peek(forwardToCache_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK_SHARED; out_msg.Sender := machineID; @@ -807,7 +807,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } action(g_sendUnblock, "g", desc="Send unblock to memory") { - enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; @@ -817,7 +817,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } action(gm_sendUnblockM, "gm", desc="Send unblock to memory and indicate M/O/E state") { - enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCKM; out_msg.Sender := machineID; @@ -827,7 +827,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } action(gs_sendUnblockS, "gs", desc="Send unblock to memory and indicate S state") { - enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCKS; @@ -993,7 +993,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } action(ll_L2toL1Transfer, "ll", desc="") { - enqueue(triggerQueue_out, TriggerMsg, latency=l2_cache_hit_latency) { + enqueue(triggerQueue_out, TriggerMsg, l2_cache_hit_latency) { out_msg.Addr := address; out_msg.Type := TriggerType:L2_to_L1; } @@ -1026,7 +1026,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") { peek(forwardToCache_in, RequestMsg) { assert(in_msg.Requestor != machineID); - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -1051,7 +1051,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(sq_sendSharedDataFromTBEToCache, "sq", desc="Send shared data from TBE to cache, still the owner") { peek(forwardToCache_in, RequestMsg) { assert(in_msg.Requestor != machineID); - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; @@ -1075,7 +1075,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") action(qm_sendDataFromTBEToCache, "qm", desc="Send data from TBE to cache, multiple sharers, still the owner") { peek(forwardToCache_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; @@ -1094,7 +1094,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } action(qq_sendDataFromTBEToMemory, "\q", desc="Send data from TBE to memory") { - enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Sender := machineID; @@ -1125,7 +1125,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } action(t_sendExclusiveDataFromTBEToMemory, "t", desc="Send exclusive data from TBE to memory") { - enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) { + enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Sender := machineID; diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm index fc9eaa06f..58e4d7346 100644 --- a/src/mem/protocol/MOESI_hammer-dir.sm +++ b/src/mem/protocol/MOESI_hammer-dir.sm @@ -492,7 +492,7 @@ machine(Directory, "AMD Hammer-like protocol") action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:WB_ACK; out_msg.Requestor := in_msg.Requestor; @@ -505,7 +505,7 @@ machine(Directory, "AMD Hammer-like protocol") action(oc_sendBlockAck, "oc", desc="Send block ack to the owner") { peek(requestQueue_in, RequestMsg) { if (((probe_filter_enabled || full_bit_dir_enabled) && (in_msg.Requestor == cache_entry.Owner)) || machineCount(MachineType:L1Cache) == 1) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:BLOCK_ACK; out_msg.Requestor := in_msg.Requestor; @@ -518,7 +518,7 @@ machine(Directory, "AMD Hammer-like protocol") action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:WB_NACK; out_msg.Requestor := in_msg.Requestor; @@ -727,7 +727,7 @@ machine(Directory, "AMD Hammer-like protocol") action(d_sendData, "d", desc="Send data to requestor") { peek(memQueue_in, MemoryMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := tbe.ResponseType; @@ -747,7 +747,7 @@ machine(Directory, "AMD Hammer-like protocol") action(dr_sendDmaData, "dr", desc="Send Data to DMA controller from memory") { peek(memQueue_in, MemoryMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) { assert(is_valid(tbe)); out_msg.PhysicalAddress := address; out_msg.LineAddress := address; @@ -765,7 +765,7 @@ machine(Directory, "AMD Hammer-like protocol") action(dt_sendDmaDataFromTbe, "dt", desc="Send Data to DMA controller from tbe") { peek(triggerQueue_in, TriggerMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) { assert(is_valid(tbe)); out_msg.PhysicalAddress := address; out_msg.LineAddress := address; @@ -782,7 +782,7 @@ machine(Directory, "AMD Hammer-like protocol") } action(da_sendDmaAck, "da", desc="Send Ack to DMA controller") { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) { assert(is_valid(tbe)); out_msg.PhysicalAddress := address; out_msg.LineAddress := address; @@ -836,7 +836,7 @@ machine(Directory, "AMD Hammer-like protocol") action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") { peek(requestQueue_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -850,7 +850,7 @@ machine(Directory, "AMD Hammer-like protocol") action(qd_queueMemoryRequestFromDmaRead, "qd", desc="Queue off-chip fetch request") { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -871,7 +871,7 @@ machine(Directory, "AMD Hammer-like protocol") fwd_set := cache_entry.Sharers; fwd_set.remove(machineIDToNodeID(in_msg.Requestor)); if (fwd_set.count() > 0) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -886,7 +886,7 @@ machine(Directory, "AMD Hammer-like protocol") } } else { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -906,7 +906,7 @@ machine(Directory, "AMD Hammer-like protocol") if (full_bit_dir_enabled) { assert(cache_entry.Sharers.count() > 0); peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := machineID; @@ -915,7 +915,7 @@ machine(Directory, "AMD Hammer-like protocol") } } } else { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := machineID; @@ -928,7 +928,7 @@ machine(Directory, "AMD Hammer-like protocol") action(io_invalidateOwnerRequest, "io", desc="invalidate all copies") { if (machineCount(MachineType:L1Cache) > 1) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; @@ -947,7 +947,7 @@ machine(Directory, "AMD Hammer-like protocol") fwd_set := cache_entry.Sharers; fwd_set.remove(machineIDToNodeID(in_msg.Requestor)); if (fwd_set.count() > 0) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -960,7 +960,7 @@ machine(Directory, "AMD Hammer-like protocol") } } } else { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -974,7 +974,7 @@ machine(Directory, "AMD Hammer-like protocol") } } else { peek(requestQueue_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { + enqueue(responseNetwork_out, ResponseMsg, 1) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -996,7 +996,7 @@ machine(Directory, "AMD Hammer-like protocol") // decouple the two. // peek(unblockNetwork_in, ResponseMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:MERGED_GETS; @@ -1017,7 +1017,7 @@ machine(Directory, "AMD Hammer-like protocol") assert(machineCount(MachineType:L1Cache) > 1); if (probe_filter_enabled || full_bit_dir_enabled) { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := in_msg.Type; @@ -1031,7 +1031,7 @@ machine(Directory, "AMD Hammer-like protocol") } } else { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -1051,7 +1051,7 @@ machine(Directory, "AMD Hammer-like protocol") if (probe_filter_enabled || full_bit_dir_enabled) { peek(requestQueue_in, RequestMsg) { if (in_msg.Requestor != cache_entry.Owner) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := in_msg.Type; @@ -1066,7 +1066,7 @@ machine(Directory, "AMD Hammer-like protocol") } } else { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -1085,7 +1085,7 @@ machine(Directory, "AMD Hammer-like protocol") assert(is_valid(tbe)); if (tbe.NumPendingMsgs > 0) { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; // @@ -1104,7 +1104,7 @@ machine(Directory, "AMD Hammer-like protocol") assert(is_valid(tbe)); if (tbe.NumPendingMsgs > 0) { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + enqueue(forwardNetwork_out, RequestMsg, memory_controller_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; // @@ -1244,7 +1244,7 @@ machine(Directory, "AMD Hammer-like protocol") action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") { peek(unblockNetwork_in, ResponseMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { assert(in_msg.Dirty); assert(in_msg.MessageSize == MessageSizeType:Writeback_Data); out_msg.Addr := address; @@ -1256,7 +1256,7 @@ machine(Directory, "AMD Hammer-like protocol") } action(ld_queueMemoryDmaWrite, "ld", desc="Write DMA data to memory") { - enqueue(memQueue_out, MemoryMsg, latency="1") { + enqueue(memQueue_out, MemoryMsg, 1) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm index fc4699fd3..1d0f67881 100644 --- a/src/mem/protocol/MOESI_hammer-dma.sm +++ b/src/mem/protocol/MOESI_hammer-dma.sm @@ -103,7 +103,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, DMARequestMsg, request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:READ; @@ -118,7 +118,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { + enqueue(reqToDirectory_out, DMARequestMsg, request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:WRITE; diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm index 54dd8bb94..885bbacbe 100644 --- a/src/mem/protocol/Network_test-cache.sm +++ b/src/mem/protocol/Network_test-cache.sm @@ -138,7 +138,7 @@ machine(L1Cache, "Network_test L1 Cache") // map_Address_to_Directory is used to retrieve it. action(a_issueRequest, "a", desc="Issue a request") { - enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(requestNetwork_out, RequestMsg, issue_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:MSG; out_msg.Requestor := machineID; @@ -149,7 +149,7 @@ machine(L1Cache, "Network_test L1 Cache") } action(b_issueForward, "b", desc="Issue a forward") { - enqueue(forwardNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(forwardNetwork_out, RequestMsg, issue_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:MSG; out_msg.Requestor := machineID; @@ -159,7 +159,7 @@ machine(L1Cache, "Network_test L1 Cache") } action(c_issueResponse, "c", desc="Issue a response") { - enqueue(responseNetwork_out, RequestMsg, latency=issue_latency) { + enqueue(responseNetwork_out, RequestMsg, issue_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:MSG; out_msg.Requestor := machineID; |