diff options
Diffstat (limited to 'src/mem/protocol')
35 files changed, 416 insertions, 416 deletions
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm index 71e81c8ae..8e44766ea 100644 --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm @@ -119,7 +119,7 @@ machine(L0Cache, "MESI Directory L0 Cache") // TBE fields structure(TBE, desc="...") { - Address addr, desc="Physical address for this TBE"; + Addr addr, desc="Physical address for this TBE"; State TBEState, desc="Transient state"; DataBlock DataBlk, desc="Buffer for the data block"; bool Dirty, default="false", desc="data is dirty"; @@ -127,10 +127,10 @@ machine(L0Cache, "MESI Directory L0 Cache") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } TBETable TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs"; @@ -139,12 +139,12 @@ machine(L0Cache, "MESI Directory L0 Cache") void unset_cache_entry(); void set_tbe(TBE a); void unset_tbe(); - void wakeUpBuffers(Address a); - void wakeUpAllBuffers(Address a); + void wakeUpBuffers(Addr a); + void wakeUpAllBuffers(Addr a); void profileMsgDelay(int virtualNetworkType, Cycles c); // inclusive cache returns L0 entries only - Entry getCacheEntry(Address addr), return_by_pointer="yes" { + Entry getCacheEntry(Addr addr), return_by_pointer="yes" { Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]); if(is_valid(Dcache_entry)) { return Dcache_entry; @@ -154,17 +154,17 @@ machine(L0Cache, "MESI Directory L0 Cache") return Icache_entry; } - Entry getDCacheEntry(Address addr), return_by_pointer="yes" { + Entry getDCacheEntry(Addr addr), return_by_pointer="yes" { Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]); return Dcache_entry; } - Entry getICacheEntry(Address addr), return_by_pointer="yes" { + Entry getICacheEntry(Addr addr), return_by_pointer="yes" { Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]); return Icache_entry; } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(TBE tbe, Entry cache_entry, Addr addr) { assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false); if(is_valid(tbe)) { @@ -175,7 +175,7 @@ machine(L0Cache, "MESI Directory L0 Cache") return State:I; } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false); // MUST CHANGE @@ -188,7 +188,7 @@ machine(L0Cache, "MESI Directory L0 Cache") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { DPRINTF(RubySlicc, "%s\n", L0Cache_State_to_permission(tbe.TBEState)); @@ -205,7 +205,7 @@ machine(L0Cache, "MESI Directory L0 Cache") return AccessPermission:NotPresent; } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); @@ -214,7 +214,7 @@ machine(L0Cache, "MESI Directory L0 Cache") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; @@ -229,7 +229,7 @@ machine(L0Cache, "MESI Directory L0 Cache") return num_functional_writes; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L0Cache_State_to_permission(state)); } diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm index e999eee05..6c8df8d75 100644 --- a/src/mem/protocol/MESI_Three_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm @@ -133,7 +133,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") // TBE fields structure(TBE, desc="...") { - Address addr, desc="Physical address for this TBE"; + Addr addr, desc="Physical address for this TBE"; State TBEState, desc="Transient state"; DataBlock DataBlk, desc="Buffer for the data block"; bool Dirty, default="false", desc="data is dirty"; @@ -141,10 +141,10 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; @@ -155,17 +155,17 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") void unset_cache_entry(); void set_tbe(TBE a); void unset_tbe(); - void wakeUpBuffers(Address a); - void wakeUpAllBuffers(Address a); + void wakeUpBuffers(Addr a); + void wakeUpAllBuffers(Addr a); void profileMsgDelay(int virtualNetworkType, Cycles c); // inclusive cache returns L1 entries only - Entry getCacheEntry(Address addr), return_by_pointer="yes" { + Entry getCacheEntry(Addr addr), return_by_pointer="yes" { Entry cache_entry := static_cast(Entry, "pointer", cache[addr]); return cache_entry; } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(TBE tbe, Entry cache_entry, Addr addr) { if(is_valid(tbe)) { return tbe.TBEState; } else if (is_valid(cache_entry)) { @@ -174,7 +174,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") return State:I; } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { // MUST CHANGE if(is_valid(tbe)) { tbe.TBEState := state; @@ -185,7 +185,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState)); @@ -202,7 +202,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") return AccessPermission:NotPresent; } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); @@ -211,7 +211,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; @@ -226,7 +226,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") return num_functional_writes; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L1Cache_State_to_permission(state)); } diff --git a/src/mem/protocol/MESI_Three_Level-msg.sm b/src/mem/protocol/MESI_Three_Level-msg.sm index 7f32f1bcd..7fe4add46 100644 --- a/src/mem/protocol/MESI_Three_Level-msg.sm +++ b/src/mem/protocol/MESI_Three_Level-msg.sm @@ -50,7 +50,7 @@ enumeration(CoherenceClass, desc="...") { // Class for messages sent between the L0 and the L1 controllers. structure(CoherenceMsg, desc="...", interface="Message") { - Address addr, desc="Physical address of the cache block"; + Addr addr, desc="Physical address of the cache block"; CoherenceClass Class, desc="Type of message (GetS, GetX, PutX, etc)"; RubyAccessMode AccessMode, desc="user/supervisor access type"; MachineID Sender, desc="What component sent this message"; diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index 7ea011e1d..184f735c7 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -134,7 +134,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") // TBE fields structure(TBE, desc="...") { - Address addr, desc="Physical address for this TBE"; + Addr addr, desc="Physical address for this TBE"; State TBEState, desc="Transient state"; DataBlock DataBlk, desc="Buffer for the data block"; bool Dirty, default="false", desc="data is dirty"; @@ -143,10 +143,10 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; @@ -159,11 +159,11 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") void unset_cache_entry(); void set_tbe(TBE a); void unset_tbe(); - void wakeUpBuffers(Address a); + void wakeUpBuffers(Addr a); void profileMsgDelay(int virtualNetworkType, Cycles c); // inclusive cache returns L1 entries only - Entry getCacheEntry(Address addr), return_by_pointer="yes" { + Entry getCacheEntry(Addr addr), return_by_pointer="yes" { Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]); if(is_valid(L1Dcache_entry)) { return L1Dcache_entry; @@ -173,17 +173,17 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") return L1Icache_entry; } - Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" { + Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" { Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]); return L1Dcache_entry; } - Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" { + Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" { Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]); return L1Icache_entry; } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(TBE tbe, Entry cache_entry, Addr addr) { assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false); if(is_valid(tbe)) { @@ -194,7 +194,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") return State:NP; } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false); // MUST CHANGE @@ -207,7 +207,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState)); @@ -224,7 +224,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") return AccessPermission:NotPresent; } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); @@ -233,7 +233,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; @@ -248,7 +248,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") return num_functional_writes; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L1Cache_State_to_permission(state)); } @@ -508,7 +508,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } } - void enqueuePrefetch(Address address, RubyRequestType type) { + void enqueuePrefetch(Addr address, RubyRequestType type) { enqueue(optionalQueue_out, RubyRequest, 1) { out_msg.LineAddress := address; out_msg.Type := type; diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm index 59aff8807..e4f719d9f 100644 --- a/src/mem/protocol/MESI_Two_Level-L2cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm @@ -129,7 +129,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") // TBE fields structure(TBE, desc="...") { - Address addr, desc="Physical address for this TBE"; + Addr addr, desc="Physical address for this TBE"; State TBEState, desc="Transient state"; DataBlock DataBlk, desc="Buffer for the data block"; bool Dirty, default="false", desc="Data is Dirty"; @@ -140,10 +140,10 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs"; @@ -152,15 +152,15 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") void unset_cache_entry(); void set_tbe(TBE a); void unset_tbe(); - void wakeUpBuffers(Address a); + void wakeUpBuffers(Addr a); void profileMsgDelay(int virtualNetworkType, Cycles c); // inclusive cache, returns L2 entries only - Entry getCacheEntry(Address addr), return_by_pointer="yes" { + Entry getCacheEntry(Addr addr), return_by_pointer="yes" { return static_cast(Entry, "pointer", L2cache[addr]); } - bool isSharer(Address addr, MachineID requestor, Entry cache_entry) { + bool isSharer(Addr addr, MachineID requestor, Entry cache_entry) { if (is_valid(cache_entry)) { return cache_entry.Sharers.isElement(requestor); } else { @@ -168,14 +168,14 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } } - void addSharer(Address addr, MachineID requestor, Entry cache_entry) { + void addSharer(Addr addr, MachineID requestor, Entry cache_entry) { assert(is_valid(cache_entry)); DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n", machineID, requestor, addr); cache_entry.Sharers.add(requestor); } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(TBE tbe, Entry cache_entry, Addr addr) { if(is_valid(tbe)) { return tbe.TBEState; } else if (is_valid(cache_entry)) { @@ -184,7 +184,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") return State:NP; } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { // MUST CHANGE if (is_valid(tbe)) { tbe.TBEState := state; @@ -195,7 +195,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState)); @@ -212,7 +212,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") return AccessPermission:NotPresent; } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); @@ -221,7 +221,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; @@ -236,13 +236,13 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") return num_functional_writes; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L2Cache_State_to_permission(state)); } } - Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr, + Event L1Cache_request_type_to_event(CoherenceRequestType type, Addr addr, MachineID requestor, Entry cache_entry) { if(type == CoherenceRequestType:GETS) { return Event:L1_GETS; diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm index e213cf060..22aabee4e 100644 --- a/src/mem/protocol/MESI_Two_Level-dir.sm +++ b/src/mem/protocol/MESI_Two_Level-dir.sm @@ -77,17 +77,17 @@ machine(Directory, "MESI Two Level directory protocol") // TBE entries for DMA requests structure(TBE, desc="TBE entries for outstanding DMA requests") { - Address PhysicalAddress, desc="physical address"; + Addr PhysicalAddress, desc="physical address"; State TBEState, desc="Transient State"; DataBlock DataBlk, desc="Data to be written (DMA write only)"; int Len, desc="..."; } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); bool functionalRead(Packet *pkt); int functionalWrite(Packet *pkt); } @@ -98,9 +98,9 @@ machine(Directory, "MESI Two Level directory protocol") void set_tbe(TBE tbe); void unset_tbe(); - void wakeUpBuffers(Address a); + void wakeUpBuffers(Addr a); - Entry getDirectoryEntry(Address addr), return_by_pointer="yes" { + Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" { Entry dir_entry := static_cast(Entry, "pointer", directory[addr]); if (is_valid(dir_entry)) { @@ -112,7 +112,7 @@ machine(Directory, "MESI Two Level directory protocol") return dir_entry; } - State getState(TBE tbe, Address addr) { + State getState(TBE tbe, Addr addr) { if (is_valid(tbe)) { return tbe.TBEState; } else if (directory.isPresent(addr)) { @@ -122,7 +122,7 @@ machine(Directory, "MESI Two Level directory protocol") } } - void setState(TBE tbe, Address addr, State state) { + void setState(TBE tbe, Addr addr, State state) { if (is_valid(tbe)) { tbe.TBEState := state; } @@ -132,7 +132,7 @@ machine(Directory, "MESI Two Level directory protocol") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(tbe.TBEState)); @@ -148,7 +148,7 @@ machine(Directory, "MESI Two Level directory protocol") return AccessPermission:NotPresent; } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); @@ -157,7 +157,7 @@ machine(Directory, "MESI Two Level directory protocol") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; @@ -170,7 +170,7 @@ machine(Directory, "MESI Two Level directory protocol") return num_functional_writes; } - void setAccessPermission(Address addr, State state) { + void setAccessPermission(Addr addr, State state) { if (directory.isPresent(addr)) { getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state)); } diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm index 63fe3366b..0caff177d 100644 --- a/src/mem/protocol/MESI_Two_Level-dma.sm +++ b/src/mem/protocol/MESI_Two_Level-dma.sm @@ -52,26 +52,26 @@ machine(DMA, "DMA Controller") MessageBuffer mandatoryQueue; State cur_state; - State getState(Address addr) { + State getState(Addr addr) { return cur_state; } - void setState(Address addr, State state) { + void setState(Addr addr, State state) { cur_state := state; } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { return AccessPermission:NotPresent; } - void setAccessPermission(Address addr, State state) { + void setAccessPermission(Addr addr, State state) { } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { error("DMA does not support functional read."); } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { error("DMA does not support functional write."); } diff --git a/src/mem/protocol/MESI_Two_Level-msg.sm b/src/mem/protocol/MESI_Two_Level-msg.sm index f63438209..738019e7b 100644 --- a/src/mem/protocol/MESI_Two_Level-msg.sm +++ b/src/mem/protocol/MESI_Two_Level-msg.sm @@ -58,7 +58,7 @@ enumeration(CoherenceResponseType, desc="...") { // RequestMsg structure(RequestMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)"; RubyAccessMode AccessMode, desc="user/supervisor access type"; MachineID Requestor , desc="What component request"; @@ -87,7 +87,7 @@ structure(RequestMsg, desc="...", interface="Message") { // ResponseMsg structure(ResponseMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)"; MachineID Sender, desc="What component sent the data"; NetDest Destination, desc="Node to whom the data is sent"; diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 442821506..3380cd7e6 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -93,10 +93,10 @@ machine(L1Cache, "MI Example L1 Cache") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } @@ -110,7 +110,7 @@ machine(L1Cache, "MI Example L1 Cache") void unset_tbe(); void profileMsgDelay(int virtualNetworkType, Cycles b); - Entry getCacheEntry(Address address), return_by_pointer="yes" { + Entry getCacheEntry(Addr address), return_by_pointer="yes" { return static_cast(Entry, "pointer", cacheMemory.lookup(address)); } @@ -127,7 +127,7 @@ machine(L1Cache, "MI Example L1 Cache") } } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(TBE tbe, Entry cache_entry, Addr addr) { if (is_valid(tbe)) { return tbe.TBEState; @@ -140,7 +140,7 @@ machine(L1Cache, "MI Example L1 Cache") } } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { if (is_valid(tbe)) { tbe.TBEState := state; @@ -151,7 +151,7 @@ machine(L1Cache, "MI Example L1 Cache") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { return L1Cache_State_to_permission(tbe.TBEState); @@ -165,13 +165,13 @@ machine(L1Cache, "MI Example L1 Cache") return AccessPermission:NotPresent; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L1Cache_State_to_permission(state)); } } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); @@ -180,7 +180,7 @@ machine(L1Cache, "MI Example L1 Cache") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm index 3a7f05f36..a22691bda 100644 --- a/src/mem/protocol/MI_example-dir.sm +++ b/src/mem/protocol/MI_example-dir.sm @@ -90,7 +90,7 @@ machine(Directory, "Directory protocol") // TBE entries for DMA requests structure(TBE, desc="TBE entries for outstanding DMA requests") { - Address PhysicalAddress, desc="physical address"; + Addr PhysicalAddress, desc="physical address"; State TBEState, desc="Transient State"; DataBlock DataBlk, desc="Data to be written (DMA write only)"; int Len, desc="..."; @@ -98,10 +98,10 @@ machine(Directory, "Directory protocol") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } // ** OBJECTS ** @@ -110,7 +110,7 @@ machine(Directory, "Directory protocol") void set_tbe(TBE b); void unset_tbe(); - Entry getDirectoryEntry(Address addr), return_by_pointer="yes" { + Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" { Entry dir_entry := static_cast(Entry, "pointer", directory[addr]); if (is_valid(dir_entry)) { @@ -122,7 +122,7 @@ machine(Directory, "Directory protocol") return dir_entry; } - State getState(TBE tbe, Address addr) { + State getState(TBE tbe, Addr addr) { if (is_valid(tbe)) { return tbe.TBEState; } else if (directory.isPresent(addr)) { @@ -132,7 +132,7 @@ machine(Directory, "Directory protocol") } } - void setState(TBE tbe, Address addr, State state) { + void setState(TBE tbe, Addr addr, State state) { if (is_valid(tbe)) { tbe.TBEState := state; @@ -154,7 +154,7 @@ machine(Directory, "Directory protocol") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { return Directory_State_to_permission(tbe.TBEState); @@ -167,13 +167,13 @@ machine(Directory, "Directory protocol") return AccessPermission:NotPresent; } - void setAccessPermission(Address addr, State state) { + void setAccessPermission(Addr addr, State state) { if (directory.isPresent(addr)) { getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state)); } } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); @@ -182,7 +182,7 @@ machine(Directory, "Directory protocol") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm index da6c5d926..4ae546d64 100644 --- a/src/mem/protocol/MI_example-dma.sm +++ b/src/mem/protocol/MI_example-dma.sm @@ -52,25 +52,25 @@ machine(DMA, "DMA Controller") MessageBuffer mandatoryQueue; State cur_state; - State getState(Address addr) { + State getState(Addr addr) { return cur_state; } - void setState(Address addr, State state) { + void setState(Addr addr, State state) { cur_state := state; } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { return AccessPermission:NotPresent; } - void setAccessPermission(Address addr, State state) { + void setAccessPermission(Addr addr, State state) { } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { error("DMA does not support functional read."); } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { error("DMA does not support functional write."); } diff --git a/src/mem/protocol/MI_example-msg.sm b/src/mem/protocol/MI_example-msg.sm index 17fcab98e..95d6ef18e 100644 --- a/src/mem/protocol/MI_example-msg.sm +++ b/src/mem/protocol/MI_example-msg.sm @@ -51,7 +51,7 @@ enumeration(CoherenceResponseType, desc="...") { // RequestMsg (and also forwarded requests) structure(RequestMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)"; MachineID Requestor, desc="Node who initiated the request"; NetDest Destination, desc="Multicast destination mask"; @@ -75,7 +75,7 @@ structure(RequestMsg, desc="...", interface="Message") { // ResponseMsg (and also unblock requests) structure(ResponseMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)"; MachineID Sender, desc="Node who sent the data"; NetDest Destination, desc="Node to whom the data is sent"; @@ -110,8 +110,8 @@ enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") { structure(DMARequestMsg, desc="...", interface="Message") { DMARequestType Type, desc="Request type (read/write)"; - Address PhysicalAddress, desc="Physical address for this request"; - Address LineAddress, desc="Line address for this request"; + Addr PhysicalAddress, desc="Physical address for this request"; + Addr LineAddress, desc="Line address for this request"; MachineID Requestor, desc="Node who initiated the request"; NetDest Destination, desc="Destination"; DataBlock DataBlk, desc="DataBlk attached to this request"; @@ -129,8 +129,8 @@ structure(DMARequestMsg, desc="...", interface="Message") { structure(DMAResponseMsg, desc="...", interface="Message") { DMAResponseType Type, desc="Response type (DATA/ACK)"; - Address PhysicalAddress, desc="Physical address for this request"; - Address LineAddress, desc="Line address for this request"; + Addr PhysicalAddress, desc="Physical address for this request"; + Addr LineAddress, desc="Line address for this request"; NetDest Destination, desc="Destination"; DataBlock DataBlk, desc="DataBlk attached to this request"; MessageSizeType MessageSize, desc="size category of the message"; diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 3543229d8..8a2eee1e2 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -115,7 +115,7 @@ machine(L1Cache, "Directory protocol") // TBE fields structure(TBE, desc="...") { - Address addr, desc="Physical address for this TBE"; + Addr addr, desc="Physical address for this TBE"; State TBEState, desc="Transient state"; DataBlock DataBlk, desc="data for the block, required for concurrent writebacks"; bool Dirty, desc="Is the data dirty (different than memory)?"; @@ -123,10 +123,10 @@ machine(L1Cache, "Directory protocol") } structure(TBETable, external ="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } void set_cache_entry(AbstractCacheEntry b); @@ -140,7 +140,7 @@ machine(L1Cache, "Directory protocol") TimerTable useTimerTable; int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; - Entry getCacheEntry(Address addr), return_by_pointer="yes" { + Entry getCacheEntry(Addr addr), return_by_pointer="yes" { Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr)); if(is_valid(L1Dcache_entry)) { return L1Dcache_entry; @@ -150,15 +150,15 @@ machine(L1Cache, "Directory protocol") return L1Icache_entry; } - Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" { + Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" { return static_cast(Entry, "pointer", L1Dcache.lookup(addr)); } - Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" { + Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" { return static_cast(Entry, "pointer", L1Icache.lookup(addr)); } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(TBE tbe, Entry cache_entry, Addr addr) { if(is_valid(tbe)) { return tbe.TBEState; } else if (is_valid(cache_entry)) { @@ -167,7 +167,7 @@ machine(L1Cache, "Directory protocol") return State:I; } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false); if (is_valid(tbe)) { @@ -189,7 +189,7 @@ machine(L1Cache, "Directory protocol") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState)); @@ -206,13 +206,13 @@ machine(L1Cache, "Directory protocol") return AccessPermission:NotPresent; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L1Cache_State_to_permission(state)); } } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { Entry cache_entry := getCacheEntry(addr); if(is_valid(cache_entry)) { testAndRead(addr, cache_entry.DataBlk, pkt); @@ -226,7 +226,7 @@ machine(L1Cache, "Directory protocol") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; Entry cache_entry := getCacheEntry(addr); @@ -265,7 +265,7 @@ machine(L1Cache, "Directory protocol") // ** IN_PORTS ** // Use Timer - in_port(useTimerTable_in, Address, useTimerTable) { + in_port(useTimerTable_in, Addr, useTimerTable) { if (useTimerTable_in.isReady()) { trigger(Event:Use_Timeout, useTimerTable.readyAddress(), getCacheEntry(useTimerTable.readyAddress()), diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm index 36278b8f0..38c6e9f9b 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -192,9 +192,9 @@ machine(L2Cache, "Token protocol") // TBE fields structure(TBE, desc="...") { - Address addr, desc="Physical address for this TBE"; + Addr addr, desc="Physical address for this TBE"; State TBEState, desc="Transient state"; - Address PC, desc="Program counter of request"; + Addr PC, desc="Program counter of request"; DataBlock DataBlk, desc="Buffer for the data block"; bool Dirty, desc="Is the data dirty (different than memory)?"; @@ -210,17 +210,17 @@ machine(L2Cache, "Token protocol") } structure(TBETable, external = "yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } structure(PerfectCacheMemory, external = "yes") { - void allocate(Address); - void deallocate(Address); - DirEntry lookup(Address); - bool isTagPresent(Address); + void allocate(Addr); + void deallocate(Addr); + DirEntry lookup(Addr); + bool isTagPresent(Addr); } TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs"; @@ -231,19 +231,19 @@ machine(L2Cache, "Token protocol") void set_tbe(TBE b); void unset_tbe(); - Entry getCacheEntry(Address address), return_by_pointer="yes" { + Entry getCacheEntry(Addr address), return_by_pointer="yes" { return static_cast(Entry, "pointer", L2cache[address]); } - bool isDirTagPresent(Address addr) { + bool isDirTagPresent(Addr addr) { return (localDirectory.isTagPresent(addr) ); } - DirEntry getDirEntry(Address address), return_by_pointer="yes" { + DirEntry getDirEntry(Addr address), return_by_pointer="yes" { return localDirectory.lookup(address); } - bool isOnlySharer(Entry cache_entry, Address addr, MachineID shar_id) { + bool isOnlySharer(Entry cache_entry, Addr addr, MachineID shar_id) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); if (cache_entry.Sharers.count() > 1) { @@ -285,7 +285,7 @@ machine(L2Cache, "Token protocol") } } - void copyCacheStateToDir(Entry cache_entry, Address addr) { + void copyCacheStateToDir(Entry cache_entry, Addr addr) { assert(localDirectory.isTagPresent(addr) == false); assert(is_valid(cache_entry)); localDirectory.allocate(addr); @@ -297,7 +297,7 @@ machine(L2Cache, "Token protocol") } - void copyDirToCache(Entry cache_entry, Address addr) { + void copyDirToCache(Entry cache_entry, Addr addr) { assert(is_valid(cache_entry)); DirEntry dir_entry := getDirEntry(addr); cache_entry.Sharers := dir_entry.Sharers; @@ -306,7 +306,7 @@ machine(L2Cache, "Token protocol") } - void recordLocalSharerInDir(Entry cache_entry, Address addr, MachineID shar_id) { + void recordLocalSharerInDir(Entry cache_entry, Addr addr, MachineID shar_id) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); cache_entry.Sharers.add(shar_id); @@ -323,7 +323,7 @@ machine(L2Cache, "Token protocol") } } - void recordNewLocalExclusiveInDir(Entry cache_entry, Address addr, MachineID exc_id) { + void recordNewLocalExclusiveInDir(Entry cache_entry, Addr addr, MachineID exc_id) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); @@ -342,7 +342,7 @@ machine(L2Cache, "Token protocol") } } - void removeAllLocalSharersFromDir(Entry cache_entry, Address addr) { + void removeAllLocalSharersFromDir(Entry cache_entry, Addr addr) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); cache_entry.Sharers.clear(); @@ -355,7 +355,7 @@ machine(L2Cache, "Token protocol") } } - void removeSharerFromDir(Entry cache_entry, Address addr, MachineID sender) { + void removeSharerFromDir(Entry cache_entry, Addr addr, MachineID sender) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); cache_entry.Sharers.remove(sender); @@ -366,7 +366,7 @@ machine(L2Cache, "Token protocol") } } - void removeOwnerFromDir(Entry cache_entry, Address addr, MachineID sender) { + void removeOwnerFromDir(Entry cache_entry, Addr addr, MachineID sender) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); cache_entry.OwnerValid := false; @@ -377,7 +377,7 @@ machine(L2Cache, "Token protocol") } } - bool isLocalSharer(Entry cache_entry, Address addr, MachineID shar_id) { + bool isLocalSharer(Entry cache_entry, Addr addr, MachineID shar_id) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); return cache_entry.Sharers.isElement(shar_id); @@ -388,7 +388,7 @@ machine(L2Cache, "Token protocol") } } - NetDest getLocalSharers(Entry cache_entry, Address addr) { + NetDest getLocalSharers(Entry cache_entry, Addr addr) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); return cache_entry.Sharers; @@ -399,7 +399,7 @@ machine(L2Cache, "Token protocol") } } - MachineID getLocalOwner(Entry cache_entry, Address addr) { + MachineID getLocalOwner(Entry cache_entry, Addr addr) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); return cache_entry.Owner; @@ -410,7 +410,7 @@ machine(L2Cache, "Token protocol") } } - int countLocalSharers(Entry cache_entry, Address addr) { + int countLocalSharers(Entry cache_entry, Addr addr) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); return cache_entry.Sharers.count(); @@ -421,7 +421,7 @@ machine(L2Cache, "Token protocol") } } - bool isLocalOwnerValid(Entry cache_entry, Address addr) { + bool isLocalOwnerValid(Entry cache_entry, Addr addr) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); return cache_entry.OwnerValid; @@ -432,7 +432,7 @@ machine(L2Cache, "Token protocol") } } - int countLocalSharersExceptRequestor(Entry cache_entry, Address addr, MachineID requestor) { + int countLocalSharersExceptRequestor(Entry cache_entry, Addr addr, MachineID requestor) { if (is_valid(cache_entry)) { assert (localDirectory.isTagPresent(addr) == false); if (cache_entry.Sharers.isElement(requestor)) { @@ -453,7 +453,7 @@ machine(L2Cache, "Token protocol") } } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(TBE tbe, Entry cache_entry, Addr addr) { if (is_valid(tbe)) { return tbe.TBEState; @@ -471,7 +471,7 @@ machine(L2Cache, "Token protocol") return CoherenceRequestType_to_string(type); } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { assert((localDirectory.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false); if (is_valid(tbe)) { @@ -518,7 +518,7 @@ machine(L2Cache, "Token protocol") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState)); @@ -535,13 +535,13 @@ machine(L2Cache, "Token protocol") return AccessPermission:NotPresent; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L2Cache_State_to_permission(state)); } } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); @@ -550,7 +550,7 @@ machine(L2Cache, "Token protocol") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm index 752f80b3a..dcd37cc33 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -102,17 +102,17 @@ machine(Directory, "Directory protocol") } structure(TBE, desc="...") { - Address PhysicalAddress, desc="Physical address for this entry"; + Addr PhysicalAddress, desc="Physical address for this entry"; int Len, desc="Length of request"; DataBlock DataBlk, desc="DataBlk"; MachineID Requestor, desc="original requestor"; } structure(TBETable, external = "yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } // ** OBJECTS ** @@ -121,7 +121,7 @@ machine(Directory, "Directory protocol") void set_tbe(TBE b); void unset_tbe(); - Entry getDirectoryEntry(Address addr), return_by_pointer="yes" { + Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" { Entry dir_entry := static_cast(Entry, "pointer", directory[addr]); if (is_valid(dir_entry)) { @@ -133,11 +133,11 @@ machine(Directory, "Directory protocol") return dir_entry; } - State getState(TBE tbe, Address addr) { + State getState(TBE tbe, Addr addr) { return getDirectoryEntry(addr).DirectoryState; } - void setState(TBE tbe, Address addr, State state) { + void setState(TBE tbe, Addr addr, State state) { if (directory.isPresent(addr)) { if (state == State:I) { @@ -174,7 +174,7 @@ machine(Directory, "Directory protocol") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { if (directory.isPresent(addr)) { DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState)); return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState); @@ -184,17 +184,17 @@ machine(Directory, "Directory protocol") return AccessPermission:NotPresent; } - void setAccessPermission(Address addr, State state) { + void setAccessPermission(Addr addr, State state) { if (directory.isPresent(addr)) { getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state)); } } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { functionalMemoryRead(pkt); } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt); return num_functional_writes; @@ -202,7 +202,7 @@ machine(Directory, "Directory protocol") // if no sharers, then directory can be considered // both a sharer and exclusive w.r.t. coherence checking - bool isBlockShared(Address addr) { + bool isBlockShared(Addr addr) { if (directory.isPresent(addr)) { if (getDirectoryEntry(addr).DirectoryState == State:I) { return true; @@ -211,7 +211,7 @@ machine(Directory, "Directory protocol") return false; } - bool isBlockExclusive(Address addr) { + bool isBlockExclusive(Addr addr) { if (directory.isPresent(addr)) { if (getDirectoryEntry(addr).DirectoryState == State:I) { return true; @@ -487,7 +487,7 @@ machine(Directory, "Directory protocol") desc="Queue off-chip writeback request") { peek(unblockNetwork_in, ResponseMsg) { DataBlock DataBlk := in_msg.DataBlk; - DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), + DataBlk.copyPartial(tbe.DataBlk, getOffset(tbe.PhysicalAddress), tbe.Len); queueMemoryWrite(tbe.Requestor, address, to_memory_controller_latency, DataBlk); diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index f534a0f62..e9931f25b 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -57,16 +57,16 @@ machine(DMA, "DMA Controller") } structure(TBE, desc="...") { - Address address, desc="Physical address"; + Addr address, desc="Physical address"; int NumAcks, default="0", desc="Number of Acks pending"; DataBlock DataBlk, desc="Data"; } structure(TBETable, external = "yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } MessageBuffer mandatoryQueue; @@ -77,25 +77,25 @@ machine(DMA, "DMA Controller") void set_tbe(TBE b); void unset_tbe(); - State getState(TBE tbe, Address addr) { + State getState(TBE tbe, Addr addr) { return cur_state; } - void setState(TBE tbe, Address addr, State state) { + void setState(TBE tbe, Addr addr, State state) { cur_state := state; } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { return AccessPermission:NotPresent; } - void setAccessPermission(Address addr, State state) { + void setAccessPermission(Addr addr, State state) { } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { error("DMA does not support functional read."); } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { error("DMA does not support functional write."); } diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm b/src/mem/protocol/MOESI_CMP_directory-msg.sm index a6693ef51..5f6f8268a 100644 --- a/src/mem/protocol/MOESI_CMP_directory-msg.sm +++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm @@ -69,7 +69,7 @@ enumeration(TriggerType, desc="...") { // TriggerMsg structure(TriggerMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; TriggerType Type, desc="Type of trigger"; bool functionalRead(Packet *pkt) { @@ -85,7 +85,7 @@ structure(TriggerMsg, desc="...", interface="Message") { // RequestMsg (and also forwarded requests) structure(RequestMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; int Len, desc="Length of Request"; CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)"; MachineID Requestor, desc="Node who initiated the request"; @@ -114,7 +114,7 @@ structure(RequestMsg, desc="...", interface="Message") { // ResponseMsg (and also unblock requests) structure(ResponseMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)"; MachineID Sender, desc="Node who sent the data"; MachineType SenderMachine, desc="type of component sending msg"; diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index bdad86cf6..af6e4c0d5 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -150,10 +150,10 @@ machine(L1Cache, "Token protocol") // TBE fields structure(TBE, desc="...") { - Address addr, desc="Physical address for this TBE"; + Addr addr, desc="Physical address for this TBE"; State TBEState, desc="Transient state"; int IssueCount, default="0", desc="The number of times we've issued a request for this line."; - Address PC, desc="Program counter of request"; + Addr PC, desc="Program counter of request"; bool WentPersistent, default="false", desc="Request went persistent"; bool ExternalResponse, default="false", desc="Response came from an external controller"; @@ -166,22 +166,22 @@ machine(L1Cache, "Token protocol") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } structure(PersistentTable, external="yes") { - void persistentRequestLock(Address, MachineID, AccessType); - void persistentRequestUnlock(Address, MachineID); - bool okToIssueStarving(Address, MachineID); - MachineID findSmallest(Address); - AccessType typeOfSmallest(Address); - void markEntries(Address); - bool isLocked(Address); - int countStarvingForAddress(Address); - int countReadStarvingForAddress(Address); + void persistentRequestLock(Addr, MachineID, AccessType); + void persistentRequestUnlock(Addr, MachineID); + bool okToIssueStarving(Addr, MachineID); + MachineID findSmallest(Addr); + AccessType typeOfSmallest(Addr); + void markEntries(Addr); + bool isLocked(Addr); + int countStarvingForAddress(Addr); + int countReadStarvingForAddress(Addr); } void set_cache_entry(AbstractCacheEntry b); @@ -189,7 +189,7 @@ machine(L1Cache, "Token protocol") void set_tbe(TBE b); void unset_tbe(); void wakeUpAllBuffers(); - void wakeUpBuffers(Address a); + void wakeUpBuffers(Addr a); Cycles curCycle(); TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; @@ -230,7 +230,7 @@ machine(L1Cache, "Token protocol") averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency; } - Entry getCacheEntry(Address addr), return_by_pointer="yes" { + Entry getCacheEntry(Addr addr), return_by_pointer="yes" { Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr)); if(is_valid(L1Dcache_entry)) { return L1Dcache_entry; @@ -240,23 +240,23 @@ machine(L1Cache, "Token protocol") return L1Icache_entry; } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; num_functional_writes := num_functional_writes + testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); return num_functional_writes; } - Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" { + Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" { Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr)); return L1Dcache_entry; } - Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" { + Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" { Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr)); return L1Icache_entry; } @@ -268,7 +268,7 @@ machine(L1Cache, "Token protocol") return 0; } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(TBE tbe, Entry cache_entry, Addr addr) { if (is_valid(tbe)) { return tbe.TBEState; @@ -284,7 +284,7 @@ machine(L1Cache, "Token protocol") } } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false); if (is_valid(tbe)) { @@ -365,7 +365,7 @@ machine(L1Cache, "Token protocol") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := L1_TBEs[addr]; if(is_valid(tbe)) { return L1Cache_State_to_permission(tbe.TBEState); @@ -379,7 +379,7 @@ machine(L1Cache, "Token protocol") return AccessPermission:NotPresent; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L1Cache_State_to_permission(state)); } @@ -414,7 +414,7 @@ machine(L1Cache, "Token protocol") } // NOTE: direct local hits should not call this function - bool isExternalHit(Address addr, MachineID sender) { + bool isExternalHit(Addr addr, MachineID sender) { if (machineIDToMachineType(sender) == MachineType:L1Cache) { return true; } else if (machineIDToMachineType(sender) == MachineType:L2Cache) { @@ -430,11 +430,11 @@ machine(L1Cache, "Token protocol") return true; } - bool okToIssueStarving(Address addr, MachineID machineID) { + bool okToIssueStarving(Addr addr, MachineID machineID) { return persistentTable.okToIssueStarving(addr, machineID); } - void markPersistentEntries(Address addr) { + void markPersistentEntries(Addr addr) { persistentTable.markEntries(addr); } @@ -457,7 +457,7 @@ machine(L1Cache, "Token protocol") // ** IN_PORTS ** // Use Timer - in_port(useTimerTable_in, Address, useTimerTable, rank=5) { + in_port(useTimerTable_in, Addr, useTimerTable, rank=5) { if (useTimerTable_in.isReady()) { TBE tbe := L1_TBEs[useTimerTable.readyAddress()]; @@ -483,7 +483,7 @@ machine(L1Cache, "Token protocol") } // Reissue Timer - in_port(reissueTimerTable_in, Address, reissueTimerTable, rank=4) { + in_port(reissueTimerTable_in, Addr, reissueTimerTable, rank=4) { if (reissueTimerTable_in.isReady()) { trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(), getCacheEntry(reissueTimerTable.readyAddress()), diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm index 161c2f278..52bd19bcc 100644 --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm @@ -129,21 +129,21 @@ machine(L2Cache, "Token protocol") } structure(PerfectCacheMemory, external="yes") { - void allocate(Address); - void deallocate(Address); - DirEntry lookup(Address); - bool isTagPresent(Address); + void allocate(Addr); + void deallocate(Addr); + DirEntry lookup(Addr); + bool isTagPresent(Addr); } structure(PersistentTable, external="yes") { - void persistentRequestLock(Address, MachineID, AccessType); - void persistentRequestUnlock(Address, MachineID); - MachineID findSmallest(Address); - AccessType typeOfSmallest(Address); - void markEntries(Address); - bool isLocked(Address); - int countStarvingForAddress(Address); - int countReadStarvingForAddress(Address); + void persistentRequestLock(Addr, MachineID, AccessType); + void persistentRequestUnlock(Addr, MachineID); + MachineID findSmallest(Addr); + AccessType typeOfSmallest(Addr); + void markEntries(Addr); + bool isLocked(Addr); + int countStarvingForAddress(Addr); + int countReadStarvingForAddress(Addr); } PersistentTable persistentTable; @@ -152,20 +152,20 @@ machine(L2Cache, "Token protocol") void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); - Entry getCacheEntry(Address address), return_by_pointer="yes" { + Entry getCacheEntry(Addr address), return_by_pointer="yes" { Entry cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address)); return cache_entry; } - DirEntry getDirEntry(Address address), return_by_pointer="yes" { + DirEntry getDirEntry(Addr address), return_by_pointer="yes" { return localDirectory.lookup(address); } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; num_functional_writes := num_functional_writes + testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); @@ -180,7 +180,7 @@ machine(L2Cache, "Token protocol") } } - State getState(Entry cache_entry, Address addr) { + State getState(Entry cache_entry, Addr addr) { if (is_valid(cache_entry)) { return cache_entry.CacheState; } else if (persistentTable.isLocked(addr)) { @@ -190,7 +190,7 @@ machine(L2Cache, "Token protocol") } } - void setState(Entry cache_entry, Address addr, State state) { + void setState(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { // Make sure the token count is in range @@ -227,7 +227,7 @@ machine(L2Cache, "Token protocol") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { Entry cache_entry := getCacheEntry(addr); if(is_valid(cache_entry)) { return L2Cache_State_to_permission(cache_entry.CacheState); @@ -236,13 +236,13 @@ machine(L2Cache, "Token protocol") return AccessPermission:NotPresent; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L2Cache_State_to_permission(state)); } } - void removeSharer(Address addr, NodeID id) { + void removeSharer(Addr addr, NodeID id) { if (localDirectory.isTagPresent(addr)) { DirEntry dir_entry := getDirEntry(addr); @@ -253,7 +253,7 @@ machine(L2Cache, "Token protocol") } } - bool sharersExist(Address addr) { + bool sharersExist(Addr addr) { if (localDirectory.isTagPresent(addr)) { DirEntry dir_entry := getDirEntry(addr); if (dir_entry.Sharers.count() > 0) { @@ -268,7 +268,7 @@ machine(L2Cache, "Token protocol") } } - bool exclusiveExists(Address addr) { + bool exclusiveExists(Addr addr) { if (localDirectory.isTagPresent(addr)) { DirEntry dir_entry := getDirEntry(addr); if (dir_entry.exclusive) { @@ -284,12 +284,12 @@ machine(L2Cache, "Token protocol") } // assumes that caller will check to make sure tag is present - Set getSharers(Address addr) { + Set getSharers(Addr addr) { DirEntry dir_entry := getDirEntry(addr); return dir_entry.Sharers; } - void setNewWriter(Address addr, NodeID id) { + void setNewWriter(Addr addr, NodeID id) { if (localDirectory.isTagPresent(addr) == false) { localDirectory.allocate(addr); } @@ -299,7 +299,7 @@ machine(L2Cache, "Token protocol") dir_entry.exclusive := true; } - void addNewSharer(Address addr, NodeID id) { + void addNewSharer(Addr addr, NodeID id) { if (localDirectory.isTagPresent(addr) == false) { localDirectory.allocate(addr); } @@ -308,7 +308,7 @@ machine(L2Cache, "Token protocol") // dir_entry.exclusive := false; } - void clearExclusiveBitIfExists(Address addr) { + void clearExclusiveBitIfExists(Addr addr) { if (localDirectory.isTagPresent(addr)) { DirEntry dir_entry := getDirEntry(addr); dir_entry.exclusive := false; diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm index e7cb68fdd..fdef75181 100644 --- a/src/mem/protocol/MOESI_CMP_token-dir.sm +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm @@ -133,20 +133,20 @@ machine(Directory, "Token protocol") } structure(PersistentTable, external="yes") { - void persistentRequestLock(Address, MachineID, AccessType); - void persistentRequestUnlock(Address, MachineID); - bool okToIssueStarving(Address, MachineID); - MachineID findSmallest(Address); - AccessType typeOfSmallest(Address); - void markEntries(Address); - bool isLocked(Address); - int countStarvingForAddress(Address); - int countReadStarvingForAddress(Address); + void persistentRequestLock(Addr, MachineID, AccessType); + void persistentRequestUnlock(Addr, MachineID); + bool okToIssueStarving(Addr, MachineID); + MachineID findSmallest(Addr); + AccessType typeOfSmallest(Addr); + void markEntries(Addr); + bool isLocked(Addr); + int countStarvingForAddress(Addr); + int countReadStarvingForAddress(Addr); } // TBE entries for DMA requests structure(TBE, desc="TBE entries for outstanding DMA requests") { - Address PhysicalAddress, desc="physical address"; + Addr PhysicalAddress, desc="physical address"; State TBEState, desc="Transient State"; DataBlock DataBlk, desc="Current view of the associated address range"; int Len, desc="..."; @@ -155,10 +155,10 @@ machine(Directory, "Token protocol") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } // ** OBJECTS ** @@ -174,7 +174,7 @@ machine(Directory, "Token protocol") void set_tbe(TBE b); void unset_tbe(); - Entry getDirectoryEntry(Address addr), return_by_pointer="yes" { + Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" { Entry dir_entry := static_cast(Entry, "pointer", directory[addr]); if (is_valid(dir_entry)) { @@ -186,7 +186,7 @@ machine(Directory, "Token protocol") return dir_entry; } - State getState(TBE tbe, Address addr) { + State getState(TBE tbe, Addr addr) { if (is_valid(tbe)) { return tbe.TBEState; } else { @@ -194,7 +194,7 @@ machine(Directory, "Token protocol") } } - void setState(TBE tbe, Address addr, State state) { + void setState(TBE tbe, Addr addr, State state) { if (is_valid(tbe)) { tbe.TBEState := state; } @@ -217,7 +217,7 @@ machine(Directory, "Token protocol") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { return Directory_State_to_permission(tbe.TBEState); @@ -232,19 +232,19 @@ machine(Directory, "Token protocol") return AccessPermission:NotPresent; } - void setAccessPermission(Address addr, State state) { + void setAccessPermission(Addr addr, State state) { getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state)); } - bool okToIssueStarving(Address addr, MachineID machinID) { + bool okToIssueStarving(Addr addr, MachineID machinID) { return persistentTable.okToIssueStarving(addr, machineID); } - void markPersistentEntries(Address addr) { + void markPersistentEntries(Addr addr) { persistentTable.markEntries(addr); } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); @@ -253,7 +253,7 @@ machine(Directory, "Token protocol") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; @@ -292,7 +292,7 @@ machine(Directory, "Token protocol") } // Reissue Timer - in_port(reissueTimerTable_in, Address, reissueTimerTable) { + in_port(reissueTimerTable_in, Addr, reissueTimerTable) { if (reissueTimerTable_in.isReady()) { trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(), TBEs[reissueTimerTable.readyAddress()]); @@ -736,7 +736,7 @@ machine(Directory, "Token protocol") peek(responseNetwork_in, ResponseMsg) { DataBlock DataBlk := tbe.DataBlk; tbe.DataBlk := in_msg.DataBlk; - tbe.DataBlk.copyPartial(DataBlk, addressOffset(tbe.PhysicalAddress), + tbe.DataBlk.copyPartial(DataBlk, getOffset(tbe.PhysicalAddress), tbe.Len); } } diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm index 5686a1438..56cfb2012 100644 --- a/src/mem/protocol/MOESI_CMP_token-dma.sm +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm @@ -54,25 +54,25 @@ machine(DMA, "DMA Controller") MessageBuffer mandatoryQueue; State cur_state; - State getState(Address addr) { + State getState(Addr addr) { return cur_state; } - void setState(Address addr, State state) { + void setState(Addr addr, State state) { cur_state := state; } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { return AccessPermission:NotPresent; } - void setAccessPermission(Address addr, State state) { + void setAccessPermission(Addr addr, State state) { } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { error("DMA does not support functional read."); } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { error("DMA does not support functional write."); } diff --git a/src/mem/protocol/MOESI_CMP_token-msg.sm b/src/mem/protocol/MOESI_CMP_token-msg.sm index c13dc7a38..05cefa7c8 100644 --- a/src/mem/protocol/MOESI_CMP_token-msg.sm +++ b/src/mem/protocol/MOESI_CMP_token-msg.sm @@ -58,7 +58,7 @@ enumeration(CoherenceResponseType, desc="...") { // PersistentMsg structure(PersistentMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; PersistentRequestType Type, desc="Type of starvation request"; MachineID Requestor, desc="Node who initiated the request"; NetDest Destination, desc="Destination set"; @@ -79,7 +79,7 @@ structure(PersistentMsg, desc="...", interface="Message") { // RequestMsg structure(RequestMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)"; MachineID Requestor, desc="Node who initiated the request"; NetDest Destination, desc="Multicast destination mask"; @@ -102,7 +102,7 @@ structure(RequestMsg, desc="...", interface="Message") { // ResponseMsg structure(ResponseMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)"; MachineID Sender, desc="Node who sent the data"; NetDest Destination, desc="Node to whom the data is sent"; @@ -136,8 +136,8 @@ enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") { structure(DMARequestMsg, desc="...", interface="Message") { DMARequestType Type, desc="Request type (read/write)"; - Address PhysicalAddress, desc="Physical address for this request"; - Address LineAddress, desc="Line address for this request"; + Addr PhysicalAddress, desc="Physical address for this request"; + Addr LineAddress, desc="Line address for this request"; MachineID Requestor, desc="Node who initiated the request"; NetDest Destination, desc="Destination"; DataBlock DataBlk, desc="DataBlk attached to this request"; @@ -155,8 +155,8 @@ structure(DMARequestMsg, desc="...", interface="Message") { structure(DMAResponseMsg, desc="...", interface="Message") { DMAResponseType Type, desc="Response type (DATA/ACK)"; - Address PhysicalAddress, desc="Physical address for this request"; - Address LineAddress, desc="Line address for this request"; + Addr PhysicalAddress, desc="Physical address for this request"; + Addr LineAddress, desc="Line address for this request"; NetDest Destination, desc="Destination"; DataBlock DataBlk, desc="DataBlk attached to this request"; MessageSizeType MessageSize, desc="size category of the message"; diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 21e8b7309..d5539e021 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -174,10 +174,10 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; @@ -187,10 +187,10 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") void set_tbe(TBE b); void unset_tbe(); void wakeUpAllBuffers(); - void wakeUpBuffers(Address a); + void wakeUpBuffers(Addr a); Cycles curCycle(); - Entry getCacheEntry(Address address), return_by_pointer="yes" { + Entry getCacheEntry(Addr address), return_by_pointer="yes" { Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address)); if(is_valid(L2cache_entry)) { return L2cache_entry; @@ -205,7 +205,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") return L1Icache_entry; } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { Entry cache_entry := getCacheEntry(addr); if(is_valid(cache_entry)) { testAndRead(addr, cache_entry.DataBlk, pkt); @@ -219,7 +219,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; Entry cache_entry := getCacheEntry(addr); @@ -235,22 +235,22 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") return num_functional_writes; } - Entry getL2CacheEntry(Address address), return_by_pointer="yes" { + Entry getL2CacheEntry(Addr address), return_by_pointer="yes" { Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address)); return L2cache_entry; } - Entry getL1DCacheEntry(Address address), return_by_pointer="yes" { + Entry getL1DCacheEntry(Addr address), return_by_pointer="yes" { Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(address)); return L1Dcache_entry; } - Entry getL1ICacheEntry(Address address), return_by_pointer="yes" { + Entry getL1ICacheEntry(Addr address), return_by_pointer="yes" { Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(address)); return L1Icache_entry; } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(TBE tbe, Entry cache_entry, Addr addr) { if(is_valid(tbe)) { return tbe.TBEState; } else if (is_valid(cache_entry)) { @@ -259,7 +259,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") return State:I; } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false); assert((L1Icache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false); assert((L1Dcache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false); @@ -273,7 +273,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { return L1Cache_State_to_permission(tbe.TBEState); @@ -287,7 +287,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") return AccessPermission:NotPresent; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { if (is_valid(cache_entry)) { cache_entry.changePermission(L1Cache_State_to_permission(state)); } @@ -448,7 +448,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") if (L2cache.cacheAvail(in_msg.LineAddress)) { trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe); } else { - Address l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress); + Addr l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress); trigger(Event:L2_Replacement, l2_victim_addr, getL2CacheEntry(l2_victim_addr), @@ -471,7 +471,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } } else { // No room in the L1, so we need to make room - Address l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress); + Addr l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress); if (L2cache.cacheAvail(l1i_victim_addr)) { // The L2 has room, so we move the line from the L1 to the L2 trigger(Event:L1_to_L2, @@ -479,7 +479,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") getL1ICacheEntry(l1i_victim_addr), TBEs[l1i_victim_addr]); } else { - Address l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr); + Addr l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr); // The L2 does not have room, so we replace a line from the L2 trigger(Event:L2_Replacement, l2_victim_addr, @@ -506,7 +506,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") if (L2cache.cacheAvail(in_msg.LineAddress)) { trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe); } else { - Address l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress); + Addr l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress); trigger(Event:L2_Replacement, l2_victim_addr, getL2CacheEntry(l2_victim_addr), @@ -528,7 +528,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } } else { // No room in the L1, so we need to make room - Address l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress); + Addr l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress); if (L2cache.cacheAvail(l1d_victim_addr)) { // The L2 has room, so we move the line from the L1 to the L2 trigger(Event:L1_to_L2, @@ -536,7 +536,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") getL1DCacheEntry(l1d_victim_addr), TBEs[l1d_victim_addr]); } else { - Address l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr); + Addr l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr); // The L2 does not have room, so we replace a line from the L2 trigger(Event:L2_Replacement, l2_victim_addr, diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm index 05d3f51aa..27794a3bd 100644 --- a/src/mem/protocol/MOESI_hammer-dir.sm +++ b/src/mem/protocol/MOESI_hammer-dir.sm @@ -158,7 +158,7 @@ machine(Directory, "AMD Hammer-like protocol") // TBE entries for DMA requests structure(TBE, desc="TBE entries for outstanding DMA requests") { - Address PhysicalAddress, desc="physical address"; + Addr PhysicalAddress, desc="physical address"; State TBEState, desc="Transient State"; CoherenceResponseType ResponseType, desc="The type for the subsequent response message"; int Acks, default="0", desc="The number of acks that the waiting response represents"; @@ -175,17 +175,17 @@ machine(Directory, "AMD Hammer-like protocol") } structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); + TBE lookup(Addr); + void allocate(Addr); + void deallocate(Addr); + bool isPresent(Addr); } void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); void set_tbe(TBE a); void unset_tbe(); - void wakeUpBuffers(Address a); + void wakeUpBuffers(Addr a); Cycles curCycle(); // ** OBJECTS ** @@ -194,7 +194,7 @@ machine(Directory, "AMD Hammer-like protocol") TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs"; - Entry getDirectoryEntry(Address addr), return_by_pointer="yes" { + Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" { Entry dir_entry := static_cast(Entry, "pointer", directory[addr]); if (is_valid(dir_entry)) { @@ -206,7 +206,7 @@ machine(Directory, "AMD Hammer-like protocol") return dir_entry; } - PfEntry getProbeFilterEntry(Address addr), return_by_pointer="yes" { + PfEntry getProbeFilterEntry(Addr addr), return_by_pointer="yes" { if (probe_filter_enabled || full_bit_dir_enabled) { PfEntry pfEntry := static_cast(PfEntry, "pointer", probeFilter.lookup(addr)); return pfEntry; @@ -214,7 +214,7 @@ machine(Directory, "AMD Hammer-like protocol") return OOD; } - State getState(TBE tbe, PfEntry pf_entry, Address addr) { + State getState(TBE tbe, PfEntry pf_entry, Addr addr) { if (is_valid(tbe)) { return tbe.TBEState; } else { @@ -227,7 +227,7 @@ machine(Directory, "AMD Hammer-like protocol") } } - void setState(TBE tbe, PfEntry pf_entry, Address addr, State state) { + void setState(TBE tbe, PfEntry pf_entry, Addr addr, State state) { if (is_valid(tbe)) { tbe.TBEState := state; } @@ -249,7 +249,7 @@ machine(Directory, "AMD Hammer-like protocol") getDirectoryEntry(addr).DirectoryState := state; } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { return Directory_State_to_permission(tbe.TBEState); @@ -262,11 +262,11 @@ machine(Directory, "AMD Hammer-like protocol") return AccessPermission:NotPresent; } - void setAccessPermission(PfEntry pf_entry, Address addr, State state) { + void setAccessPermission(PfEntry pf_entry, Addr addr, State state) { getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state)); } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); @@ -275,7 +275,7 @@ machine(Directory, "AMD Hammer-like protocol") } } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm index 24e41ed48..72125d157 100644 --- a/src/mem/protocol/MOESI_hammer-dma.sm +++ b/src/mem/protocol/MOESI_hammer-dma.sm @@ -52,25 +52,25 @@ machine(DMA, "DMA Controller") MessageBuffer mandatoryQueue; State cur_state; - State getState(Address addr) { + State getState(Addr addr) { return cur_state; } - void setState(Address addr, State state) { + void setState(Addr addr, State state) { cur_state := state; } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { return AccessPermission:NotPresent; } - void setAccessPermission(Address addr, State state) { + void setAccessPermission(Addr addr, State state) { } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { error("DMA does not support functional read."); } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { error("DMA does not support functional write."); } diff --git a/src/mem/protocol/MOESI_hammer-msg.sm b/src/mem/protocol/MOESI_hammer-msg.sm index 446ae14a7..326290386 100644 --- a/src/mem/protocol/MOESI_hammer-msg.sm +++ b/src/mem/protocol/MOESI_hammer-msg.sm @@ -71,7 +71,7 @@ enumeration(TriggerType, desc="...") { // TriggerMsg structure(TriggerMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; TriggerType Type, desc="Type of trigger"; bool functionalRead(Packet *pkt) { @@ -87,7 +87,7 @@ structure(TriggerMsg, desc="...", interface="Message") { // RequestMsg (and also forwarded requests) structure(RequestMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)"; MachineID Requestor, desc="Node who initiated the request"; NetDest MergedRequestors, desc="Merge set of read requestors"; @@ -114,7 +114,7 @@ structure(RequestMsg, desc="...", interface="Message") { // ResponseMsg (and also unblock requests) structure(ResponseMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)"; MachineID Sender, desc="Node who sent the data"; MachineID CurOwner, desc="current owner of the block, used for UnblockS responses"; @@ -166,8 +166,8 @@ enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") { structure(DMARequestMsg, desc="...", interface="Message") { DMARequestType Type, desc="Request type (read/write)"; - Address PhysicalAddress, desc="Physical address for this request"; - Address LineAddress, desc="Line address for this request"; + Addr PhysicalAddress, desc="Physical address for this request"; + Addr LineAddress, desc="Line address for this request"; MachineID Requestor, desc="Node who initiated the request"; NetDest Destination, desc="Destination"; DataBlock DataBlk, desc="DataBlk attached to this request"; @@ -185,8 +185,8 @@ structure(DMARequestMsg, desc="...", interface="Message") { structure(DMAResponseMsg, desc="...", interface="Message") { DMAResponseType Type, desc="Response type (DATA/ACK)"; - Address PhysicalAddress, desc="Physical address for this request"; - Address LineAddress, desc="Line address for this request"; + Addr PhysicalAddress, desc="Physical address for this request"; + Addr LineAddress, desc="Line address for this request"; NetDest Destination, desc="Destination"; DataBlock DataBlk, desc="DataBlk attached to this request"; MessageSizeType MessageSize, desc="size category of the message"; diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm index 818e6461f..43331d8f2 100644 --- a/src/mem/protocol/Network_test-cache.sm +++ b/src/mem/protocol/Network_test-cache.sm @@ -95,30 +95,30 @@ machine(L1Cache, "Network_test L1 Cache") } - State getState(Entry cache_entry, Address addr) { + State getState(Entry cache_entry, Addr addr) { return State:I; } - void setState(Entry cache_entry, Address addr, State state) { + void setState(Entry cache_entry, Addr addr, State state) { } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { return AccessPermission:NotPresent; } - void setAccessPermission(Entry cache_entry, Address addr, State state) { + void setAccessPermission(Entry cache_entry, Addr addr, State state) { } - Entry getCacheEntry(Address address), return_by_pointer="yes" { + Entry getCacheEntry(Addr address), return_by_pointer="yes" { return OOD; } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { error("Network test does not support functional read."); } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { error("Network test does not support functional write."); } diff --git a/src/mem/protocol/Network_test-dir.sm b/src/mem/protocol/Network_test-dir.sm index 40310ef62..d618e98ff 100644 --- a/src/mem/protocol/Network_test-dir.sm +++ b/src/mem/protocol/Network_test-dir.sm @@ -61,26 +61,26 @@ machine(Directory, "Network_test Directory") } // ** OBJECTS ** - State getState(Address addr) { + State getState(Addr addr) { return State:I; } - void setState(Address addr, State state) { + void setState(Addr addr, State state) { } - AccessPermission getAccessPermission(Address addr) { + AccessPermission getAccessPermission(Addr addr) { return AccessPermission:NotPresent; } - void setAccessPermission(Address addr, State state) { + void setAccessPermission(Addr addr, State state) { } - void functionalRead(Address addr, Packet *pkt) { + void functionalRead(Addr addr, Packet *pkt) { error("Network test does not support functional read."); } - int functionalWrite(Address addr, Packet *pkt) { + int functionalWrite(Addr addr, Packet *pkt) { error("Network test does not support functional write."); } diff --git a/src/mem/protocol/Network_test-msg.sm b/src/mem/protocol/Network_test-msg.sm index eb61a4ecc..7bc2e396d 100644 --- a/src/mem/protocol/Network_test-msg.sm +++ b/src/mem/protocol/Network_test-msg.sm @@ -34,7 +34,7 @@ enumeration(CoherenceRequestType, desc="...") { // RequestMsg (and also forwarded requests) structure(RequestMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)"; MachineID Requestor, desc="Node who initiated the request"; NetDest Destination, desc="Multicast destination mask"; diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/protocol/RubySlicc_ComponentMapping.sm index afb758b68..a72492b42 100644 --- a/src/mem/protocol/RubySlicc_ComponentMapping.sm +++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm @@ -30,14 +30,14 @@ // Mapping functions int machineCount(MachineType machType); -MachineID mapAddressToRange(Address addr, MachineType type, +MachineID mapAddressToRange(Addr addr, MachineType type, int low, int high); -MachineID mapAddressToRange(Address addr, MachineType type, +MachineID mapAddressToRange(Addr addr, MachineType type, int low, int high, NodeID n); NetDest broadcast(MachineType type); -MachineID map_Address_to_DMA(Address addr); -MachineID map_Address_to_Directory(Address addr); -NodeID map_Address_to_DirectoryNode(Address addr); +MachineID map_Address_to_DMA(Addr addr); +MachineID map_Address_to_Directory(Addr addr); +NodeID map_Address_to_DirectoryNode(Addr addr); NodeID machineIDToNodeID(MachineID machID); NodeID machineIDToVersion(MachineID machID); MachineType machineIDToMachineType(MachineID machID); diff --git a/src/mem/protocol/RubySlicc_Defines.sm b/src/mem/protocol/RubySlicc_Defines.sm index d25250864..d4f7fa58f 100644 --- a/src/mem/protocol/RubySlicc_Defines.sm +++ b/src/mem/protocol/RubySlicc_Defines.sm @@ -35,10 +35,10 @@ NodeID clusterID; // Functions implemented in the AbstractController class for // making timing access to the memory maintained by the // memory controllers. -void queueMemoryRead(MachineID id, Address addr, Cycles latency); -void queueMemoryWrite(MachineID id, Address addr, Cycles latency, +void queueMemoryRead(MachineID id, Addr addr, Cycles latency); +void queueMemoryWrite(MachineID id, Addr addr, Cycles latency, DataBlock block); -void queueMemoryWritePartial(MachineID id, Address addr, Cycles latency, +void queueMemoryWritePartial(MachineID id, Addr addr, Cycles latency, DataBlock block, int size); // Functions implemented in the AbstractController class for diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index 1d591482d..b643a3da1 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -35,7 +35,7 @@ external_type(uint32_t, primitive="yes"); external_type(uint64, primitive="yes"); external_type(PacketPtr, primitive="yes"); external_type(Packet, primitive="yes"); -external_type(Address); +external_type(Addr, primitive="yes"); external_type(Cycles, primitive="yes", default="Cycles(0)"); structure(DataBlock, external = "yes", desc="..."){ @@ -43,8 +43,8 @@ structure(DataBlock, external = "yes", desc="..."){ void copyPartial(DataBlock, int, int); } -bool testAndRead(Address addr, DataBlock datablk, Packet *pkt); -bool testAndWrite(Address addr, DataBlock datablk, Packet *pkt); +bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt); +bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt); // AccessPermission // The following five states define the access permission of all memory blocks. @@ -215,10 +215,10 @@ enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") { // CacheMsg structure(SequencerMsg, desc="...", interface="Message") { - Address LineAddress, desc="Line address for this request"; - Address PhysicalAddress, desc="Physical address for this request"; + Addr LineAddress, desc="Line address for this request"; + Addr PhysicalAddress, desc="Physical address for this request"; SequencerRequestType Type, desc="Type of request (LD, ST, etc)"; - Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; + Addr ProgramCounter, desc="Program counter of the instruction that caused the miss"; RubyAccessMode AccessMode, desc="user/supervisor access type"; DataBlock DataBlk, desc="Data"; int Len, desc="size in bytes of access"; diff --git a/src/mem/protocol/RubySlicc_MemControl.sm b/src/mem/protocol/RubySlicc_MemControl.sm index e71e80dc4..f211789be 100644 --- a/src/mem/protocol/RubySlicc_MemControl.sm +++ b/src/mem/protocol/RubySlicc_MemControl.sm @@ -51,7 +51,7 @@ enumeration(MemoryRequestType, desc="...") { // Message to and from Memory Control structure(MemoryMsg, desc="...", interface="Message") { - Address addr, desc="Physical address for this request"; + Addr addr, desc="Physical address for this request"; MemoryRequestType Type, desc="Type of memory request (MEMORY_READ or MEMORY_WB)"; MachineID Sender, desc="What component sent the data"; MachineID OriginalRequestorMachId, desc="What component originally requested"; diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index aaae7d2be..d032adfd8 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -98,30 +98,30 @@ structure (NetDest, external = "yes", non_obj="yes") { } structure (Sequencer, external = "yes") { - void readCallback(Address, DataBlock); - void readCallback(Address, DataBlock, bool); - void readCallback(Address, DataBlock, bool, MachineType); - void readCallback(Address, DataBlock, bool, MachineType, + void readCallback(Addr, DataBlock); + void readCallback(Addr, DataBlock, bool); + void readCallback(Addr, DataBlock, bool, MachineType); + void readCallback(Addr, DataBlock, bool, MachineType, Cycles, Cycles, Cycles); - void writeCallback(Address, DataBlock); - void writeCallback(Address, DataBlock, bool); - void writeCallback(Address, DataBlock, bool, MachineType); - void writeCallback(Address, DataBlock, bool, MachineType, + void writeCallback(Addr, DataBlock); + void writeCallback(Addr, DataBlock, bool); + void writeCallback(Addr, DataBlock, bool, MachineType); + void writeCallback(Addr, DataBlock, bool, MachineType, Cycles, Cycles, Cycles); - void checkCoherence(Address); - void evictionCallback(Address); + void checkCoherence(Addr); + void evictionCallback(Addr); void recordRequestType(SequencerRequestType); - bool checkResourceAvailable(CacheResourceType, Address); - void invalidateSC(Address); + bool checkResourceAvailable(CacheResourceType, Addr); + void invalidateSC(Addr); } structure(RubyRequest, desc="...", interface="Message", external="yes") { - Address LineAddress, desc="Line address for this request"; - Address PhysicalAddress, desc="Physical address for this request"; + Addr LineAddress, desc="Line address for this request"; + Addr PhysicalAddress, desc="Physical address for this request"; RubyRequestType Type, desc="Type of request (LD, ST, etc)"; - Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; + Addr ProgramCounter, desc="Program counter of the instruction that caused the miss"; RubyAccessMode AccessMode, desc="user/supervisor access type"; int Size, desc="size in bytes of access"; PrefetchBit Prefetch, desc="Is this a prefetch request"; @@ -133,10 +133,10 @@ structure(AbstractEntry, primitive="yes", external = "yes") { } structure (DirectoryMemory, external = "yes") { - AbstractEntry allocate(Address, AbstractEntry); - AbstractEntry lookup(Address); - bool isPresent(Address); - void invalidateBlock(Address); + AbstractEntry allocate(Addr, AbstractEntry); + AbstractEntry lookup(Addr); + bool isPresent(Addr); + void invalidateBlock(Addr); void recordRequestType(DirectoryRequestType); } @@ -145,23 +145,23 @@ structure(AbstractCacheEntry, primitive="yes", external = "yes") { } structure (CacheMemory, external = "yes") { - bool cacheAvail(Address); - Address cacheProbe(Address); - AbstractCacheEntry allocate(Address, AbstractCacheEntry); - AbstractCacheEntry allocate(Address, AbstractCacheEntry, bool); - void allocateVoid(Address, AbstractCacheEntry); - void deallocate(Address); - AbstractCacheEntry lookup(Address); - bool isTagPresent(Address); + bool cacheAvail(Addr); + Addr cacheProbe(Addr); + AbstractCacheEntry allocate(Addr, AbstractCacheEntry); + AbstractCacheEntry allocate(Addr, AbstractCacheEntry, bool); + void allocateVoid(Addr, AbstractCacheEntry); + void deallocate(Addr); + AbstractCacheEntry lookup(Addr); + bool isTagPresent(Addr); Cycles getTagLatency(); Cycles getDataLatency(); - void setMRU(Address); - void recordRequestType(CacheRequestType, Address); - bool checkResourceAvailable(CacheResourceType, Address); + void setMRU(Addr); + void recordRequestType(CacheRequestType, Addr); + bool checkResourceAvailable(CacheResourceType, Addr); int getCacheSize(); int getNumBlocks(); - Address getAddressAtIdx(int); + Addr getAddressAtIdx(int); Scalar demand_misses; Scalar demand_hits; @@ -179,25 +179,25 @@ structure (DMASequencer, external = "yes") { structure (TimerTable, inport="yes", external = "yes") { bool isReady(); - Address readyAddress(); - void set(Address, Cycles); - void unset(Address); - bool isSet(Address); + Addr readyAddress(); + void set(Addr, Cycles); + void unset(Addr); + bool isSet(Addr); } structure (GenericBloomFilter, external = "yes") { void clear(int); - void increment(Address, int); - void decrement(Address, int); - void set(Address, int); - void unset(Address, int); + void increment(Addr, int); + void decrement(Addr, int); + void set(Addr, int); + void unset(Addr, int); - bool isSet(Address, int); - int getCount(Address, int); + bool isSet(Addr, int); + int getCount(Addr, int); } structure (Prefetcher, external = "yes") { - void observeMiss(Address, RubyRequestType); - void observePfHit(Address); - void observePfMiss(Address); + void observeMiss(Addr, RubyRequestType); + void observePfHit(Addr); + void observePfMiss(Addr); } diff --git a/src/mem/protocol/RubySlicc_Util.sm b/src/mem/protocol/RubySlicc_Util.sm index ad06c4e41..9e78be65f 100644 --- a/src/mem/protocol/RubySlicc_Util.sm +++ b/src/mem/protocol/RubySlicc_Util.sm @@ -35,11 +35,11 @@ int random(int number); Cycles zero_time(); NodeID intToID(int nodenum); int IDToInt(NodeID id); -int addressToInt(Address addr); +int addressToInt(Addr addr); void procProfileCoherenceRequest(NodeID node, bool needCLB); void dirProfileCoherenceRequest(NodeID node, bool needCLB); int max_tokens(); -Address setOffset(Address addr, int offset); -Address makeLineAddress(Address addr); -int addressOffset(Address addr); +Addr setOffset(Addr addr, int offset); +Addr makeLineAddress(Addr addr); +int getOffset(Addr addr); int mod(int val, int mod); |